List of further Publications and Patents
Publications in 2010
* D. Hori, M. Miyake, N. Sadachika, H.J. Mattausch, M. Miura-Mattausch,
T. Iizuka, T. Hoshida, K.
Matsuzawa, Y. Sahara, and T. Tsukada, “Effect of
Carrier Transit Delay on Complementary Metal-Oxide-Semiconductor Switching
Performance”, Jpn. J. Appl. Phys., Vol. 49, No. 4,
Art. 04DC15 (2010.4)
* H.J. Mattausch, N. Sadachika, M. Yokomichi, M.
Miyake, T. Kajiwara, Y. Oritsuki,
T. Sakuda, H. Kikuchihara,
U. Feldmann, and M. Miura-Mattausch,
“POWER/HVMOS Devices Compact Modeling, Chapter 2, HiSIM-HV:
A Scalable, Surface-Potential-Based Compact Model for Symmetric and Asymmetric
High-Voltage MOSFETs”, New York: Springer Science+Business
Media, ISBN-13: 978-9048130450 (2010.6)
* K. Johguchi,
A. Kaya, S. Izumi, H.J. Mattausch, T. Koide, and N. Sadachika, “Process Variation Analysis Based on Ring
Oscillator Measurements and Surface Potential MOSFET Model HiSIM”, IEEE Design & Test of Computers, Vol. 27,
No. 5, 6-13 (2010.10)
* Y. Oritsuki,
M. Yokomichi, T. Kajiwara, A. Tanaka, N. Sadachika, M. Miyake, H. Kikuchihara,
K. Johguchi, U. Feldmann, H.J. Mattausch,
and M. Miura-Mattausch, “HiSIM-HV:
A Compact Model for Simulation of High-Voltage MOSFET Circuits”, IEEE Trans. on
Electron Devices 57, No. 10, 2671-2678 (2010.10)
* A. Ahmadi,
H.J. Mattausch,
M. Saeidi, M.A. Abedin, and
T. Koide, “An
Associative Memory Based Learning Model with an Efficient Hardware
Implementation in FPGA”, Expert Systems with
Applications, in press
(2010.)
* T. Kurafuji, M. Haraguchi,
M. Nakajima, T. Gyoten, T. Nishijima,
H. Yamasaki, Y. Imai, M. Ishizaki, T. Kumaki, T. Koide, H.J.
Mattausch, K. Arimoto,
“A scalable massively parallel processor for real-time image processing,” IEEE
International Solid-State Circuits Conference, Digest of Tech. Papers
(ISSCC‘2010), 334-335 (2010.2)
* T. Kumaki, H. Hiramoto,
T. Koide, and H.J. Mattausch,
“Realization of Efficient and Low-Power Parallel Face-Detection with
Massive-Parallel Memory-Embedded SIMD Matrix”, Proceedings of 53rd
IEEE International Midwest Symposium on Circuits and Systems (MWSCAS’2010),
359-362 (2010.8).
* H.J. Mattausch, W. Imafuku, T. Ansari,
A. Kawabata, and T. Koide, “Low-Power Word-Parallel Nearest-Hamming-Distance
Search Circuit based on Frequency Mapping”, Proceedings of the 36th European
Solid-State Circuits Conference (ESSCIRC‘2010), Seville, Spain, September
14-16, 538-541 (2010.9)
* M. Yasuda, T. Ansari, W. Imafuku, A. Kawabata, T. Koide, and H.J. Mattausch, “Low-Complexity
Time-Domain Winner-Take-All Circuit with High Time-Difference Resolution
Limited only by With-In-Die Variation”, Extended Abstracts of the 2010
International Conference on Solid State Devices and Materials (SSDM’2010),
1164-1165 (2010.9)
* T. Ansari, W. Imafuku,
A. Kawabata, M. Yasuda, T. Koide, and H.J.
Mattausch, “Analysis of Within-Die and Die-to-Die
CMOS-Process Variation with Reconfigurable Ring-Oscillator Arrays”, Extended
Abstracts of the 2010 International Conference on Solid State Devices and
Materials (SSDM’2010), 802-803 (2010.9)
* T. Saito, T. Tanaka, T. Hayashi, K. Kikuchihara,
T. Kanamoto, H. Masuda, M. Miyake, S. Amakawa, H.J. Mattausch and M. Miura-Mattausch,
“Modeling of RESURF LDMOS for Accurate Prediction of Junction Condition on
Device Characteristics”, Extended Abstracts of the 2010 International
Conference on Solid State Devices and Materials (SSDM’2010), 163-164 (2010.9)
* A. Kawabata, T. Koide, and
H.J. Mattausch,
“Optimization Vector Quantization by Adaptive Associative-Memory- Based
Codebook Learning in Combination with Huffman Coding”, Proceedings of the 1st International Conference on
Networking and Computing (ICNC‘2010), 15-19 (2010.11)
* T. Koide, R. Kimura,
T. Sugahara, K. Okazaki and H.J.
Mattausch, “Architecture and FPGA-Implementation of
Scalable Picture Segmentation by 2D Scanning with Flexible Pixel-Block Size”, Proceedings of the 1st International Conference on Networking and Computing (ICNC‘2010), 128-132 (2010.11)
Publications in 2009
*
K. Okazaki, K. Awane, N. Nagaoka, T. Sugahara, T. Koide, and H. J. Mattausch, “Low-Power
Silicon-Area-Efficient Image Segmentation Based on a Pixel-Block Scanning
Architecture”, Jpn. J. Appl. Phys., Vol. 48, No. 4,
Art. 04C078 (2009.4)
* M.
Miyake, D. Hori, N. Sadachika, U. Feldmann,
M. Miura-Mattausch, H. J. Mattausch, T. Iizuka,
K. Matsuzawa, Y. Sahara, T. Hoshida, and T. Tsukada, “Non-Quasi-Static Carrier Dynamics of MOSFETs
under Low-Voltage Operation”, IEICE Trans. on Electronics, vol. E92-C, No. 5, 608-615 (2009.5)
* M. Miyake, D. Hori, N. Sadachika, U. Feldmann, M. Miura-Mattausch, H. J. Mattausch, T. Ohguro, T. Iizuka, M.Taguchi, S. Kumashiro, and S. Miyamoto, “Degraded Frequency-Tuning
Range and Oscillation Amplitude of LC-VCOs due to the NQS Effect in MOS Varactors”, IEICE Trans. on Electronics, vol. E92-C,
No. 6, 777-784 (2009.6)
* H.J. Mattausch, N. Sadachika, A. Yumisaki, A. Kaya, W. Imafuku, K. Johguchi, T. Koide,
and M. Miura-Mattausch, “Correlating Microscopic and
Macroscopic Variation with Surface-Potential Compact Model”, IEEE Electron
Device Letters 30, 873-875 (2009.8)
* H.J. Mattausch, A. Yumisaki, N. Sadachika, A. Kaya, K. Johguchi, T. Koide, and M. Miura-Mattausch,
“Variation Analysis of CMOS Technologies Using Surface-Potential MOSFET Model”,
Journal of Telecommunications and Information Technology 4/2009, 37-44
(2009.12), Invited Paper
* S. Kusu, K. Ishimura, K. Ohyama, T. Miyoshi,
N. Sadachika, T. Murakami, M. Ando, H.J. Mattausch,
M. Miura-Mattausch, S. Baba, and J. Ida, “HiSIM-SOI: A Dynamic Depletion Model Valid for Device and
Circuit Optimization“, Proceedings of the 6th International Workshop on Compact
Modeling (IWCM‘2009), 13-16 (2009.1)
* T. Miyoshi, S. Kusu, T. Minami, M. Miyake,
N. Sadachika, H.J.
Mattausch, and M. Miura-Mattausch,
“Analysis and Modeling of p-i-n Photodiode Noise“,
Proceedings of the 6th International Workshop on Compact Modeling (IWCM‘2009),
71-74 (2009.1)
* T. Kajiwara, M. Miyake, N. Sadachika, H. Kikichihara, U. Feldmann, H.J. Mattausch, and M. Miura-Mattausch,
“Spatial Distribution Analysis of Self-Heating Effect in High-Voltage MOSFETs”,
Proceedings of the 2009 IEEE Applied Power Electronics Conference and
Exposition (APEC ’2008), 1687-1691 (2009.2)
* N. Nagaoka, K. Okazaki, T. Sugahara, T. Koide, and H.J. Mattausch, “Grouping Method based on
Feature Matching for Tracking and Recognition of Complex Objects”, Proceedings
of International Symposium on Intelligent Signal Processing and Communication
Systems (ISPACS’2008), 421-424, (2009.2).
* K. Okazaki, N. Nagaoka, T. Sugahara, T. Koide and H.J.
Mattausch, “Low Power and Area Efficient Image
Segmentation VLSI Architecture Using 2-Dimensional Pixel-Block Scanning”,
Proceedings of International Symposium on Intelligent Signal Processing and
Communication Systems (ISPACS’2008), 441-444, (2009.2).
* T. Kumaki, M. Tagami,
Y. Imai, T. Koide, and H.J. Mattausch, “A Ternary Multi-Ported Content Addressable
Memory Architecture utilizing Asynchronous Multiple Search-Operation
Technology”, 15th Workshop on Synthesis and System Integration of Mixed
Information Technologies (SASIMI’2009), 224-229 (2009.3)
* T. Sugahara, K. Okazaki, N. Nagaoka, R. Kimura, T. Koide, and H.J. Mattausch, “Improved Region-Growing
Image-Segmentation Algorithm Based on HSV Color Space”, 15th Workshop on
Synthesis and System Integration of Mixed Information Technologies
(SASIMI’2009), 167-171 (2009.3)
* A. Kaya, K. Johguchi,
S. Izumi, H.J. Mattausch,
and T. Koide “Analysis of Process
Variations in 90-nm CMOS Technology with Ring Oscillators”, 15th Workshop on
Synthesis and System Integration of Mixed Information Technologies
(SASIMI’2009), 446-449 (2009.3)
* S. Sakakibara, W. Imafuku,
A. Kawabata, T. Ansari, H.J. Mattausch, and T. Koide, “VLSI
Design of a Handwritten-Character Learning and Recognition system based on
Associative Memory”, 15th Workshop on Synthesis and System Integration of Mixed
Information Technologies (SASIMI’2009), 161-166 (2009.3)
* Y. Oritsuki, T. Sakuda,
N. Sadachika, M. Miyake, T. Kajiwara, U. Feldmann, H.J. Mattausch,
and M. Miura-Mattausch, “High-Voltage MOSFET Model
Valid for Device Optimization”, Proceedings of the 2009 NIST Nanotechnology
Conference and Trade Show (NIST-Nanotech ’2009), 600-603 (2009.5)
* H.J.
Mattausch, A. Yumisaki,
N. Sadachika, A. Kaya, K. Johguchi, T. Koide, and M. Miura-Mattausch,,
“Variation Analysis of CMOS Technologies Using Surface-Potential MOSFET Model”,
Proceedings of the 8th International Symposium on Diagnostics & Yield
(D&Y’2009), (2009.6), Invited
Presentation
* H.J.
Mattausch, N. Sadachika,
S. Kusu, K. Ishimura, T.
Murakami, M. Ando, and M. Miura-Mattausch,
“Surface-Potential-Based Compact Model HiSIM-SOI for
Silicon-On-Insulator MOSFETs”, Proceedings of the 16th International Conference
on Mixed Design of Integrated Circuits and Systems (MIXDES’2009), 77-81
(2009.6), Invited Paper
* T. Sakuda,
N. Sadachika, Y. Oritsuki,
M. Yokomichi, M. Miyake, T. Kajiwara, H. Kikuchihara, U. Feldmann, H.J. Mattausch,
and M. Miura-Mattausch, “Effect of
Impact-Ionization-Generated Holes on the Breakdown Mechanism in LDMOS Devices”,
Proceedings of the IEEE International Conference on Simulation of Semiconductor
Processes and Devices (SISPAD’2009), Art. 11-3, 1-4 (2009.9)
* K. Johguchi,
A. Kaya, S. Izumi, H.J. Mattausch, T. Koide, and N. Sadachika, “Within-Die/Wafer Variation Analysis of Basic
CMOS Circuits based on Surface-Potential-Model HiSIM2”, Extended Abstracts of
the 2009 International Conference on Solid State Devices and Materials
(SSDM’2009), 1072-1073 (2009.10)
* Y. Imai, T. Kumaki, T. Koide, and H.J.
Mattausch, “High-Speed Face Detection in Images
with Massive-Parallel Bit-Serial SIMD Processor Using Haar-Like
Features”, Extended Abstracts of the 2009 International Conference on Solid
State Devices and Materials (SSDM’2009), 464-465 (2009.10)
* D. Hori, M. Miyake, N. Sadachika, H.J. Mattausch, M. Miura-Mattausch,
T. Iizuka, T. Hoshida, K.
Matsuzawa, S. Sahara, and T. Tsukada, “Influence of
Carrier Transit Delay on CMOS Switching Performance”, Extended Abstracts of the
2009 International Conference on Solid State Devices and Materials (SSDM’2009),
777-778 (2009.10)
* T. Hayashi, N. Sadachika, T. Murakami, D. Sugiyama, S. Yukuta,
S. Kusu, K. Johguchi, M.
Miyake, H.J. Mattausch,
M. Miura-Mattausch, S. Baba, and J. Ida, “Modeling of
Electron Tunneling in SOI-MOSFET and Its Influence on Device Characteristics”,
Proceedings of the 35th 2009 IEEE International SOI Conference (SOI’2009),
Art. 8.5, 1-2 (2009.10)
* W. Imafuku,
S. Sakakibara, A. Kawabata, T. Ansari,
H.J. Mattausch,
and T. Koide, “Associative-Memory-Based Prototype LSI with Recognition and
On-line Learning Capability and its Application to Handwritten Characters”, Proceedings
of International Symposium on Intelligent Signal Processing and Communication
Systems (ISPACS’2009), 627-630 (2009.12).
* H.J.
Mattausch, K. Johguchi,
T. Kumaki, and T. Koide, “The Role of Functional
Memories in Parallel Information Processing with Localized and Distributed
Systems”, 10th International Conference on Parallel and Distributed Computing,
Applications and Technologies (PDCAT‘2009), (2009.12), Invited Keynote Presentation
* T. Kumaki, Y. Imai, T. Koide, and H.J. Mattausch,
“VLSI-Architecture for Enabling Multiple Parallel Associative Searches with
Standard SRAM Macros”, Proceedings of International Symposium on Intelligent
Signal Processing and Communication Systems (ISPACS’2009), 45-48 (2009.12).
Publications in 2008
* T. Kumaki, M. Ishizaki, T. Koide, H.J. Mattausch, Y. Kuroda, T. Gyohten, H. Noda, K. Dosaka, K. Arimoto, and K. Saito, "Integration Architecture of Content Addressable Memory and Massive-Parallel Memory-Embedded SIMD Matrix for Versatile Multimedia Processor", IEICE Trans. on Electronics, vol. E91-C, 1409-1418 (2008)
* T. Minami, Y. Takeda, M. Miyake, M. Miura-Mattausch, H. J. Mattausch, T. Ohguro, T. Iizuka, M.Taguchi, and S. Miyamoto, "Frequency Dependence of Measured Metal Oxide Semiconductor Field-Effect Transistor Distortion Characteristic", Jpn. J. Appl. Phys., Vol. 47, No. 4, 2610-2615 (2008)
* M. Yokomichi, N. Sadachika, M. Miyake, T. Kajiwara, H. J. Mattausch, and M. Miura-Mattausch, "Laterally Diffused Metal Oxide Semiconductor Model for Device and Circuit Optimization", Jpn. J. Appl. Phys., Vol. 47, No. 4, 2560-2563 (2008)
* H.J. Mattausch, T. Kajiwara, M. Yokomichi, T. Sakuda, Y. Oritsuki, M. Miyake, N. Sadachika, H. Kikuchihara, U. Feldmann, and M. Miura-Mattausch, " HiSIM-HV: A Compact Model for Simulation of High-Voltage-MOSFET Circuits ", Proceedings of the International Conference on Solid-State and Integrated-Circuit Technology (ICSICT'2008), B1.5 (2008), Invited Paper
* S. Kusu, K. Ishimura, K. Ohyama, T. Miyoshi, D. Hori, N. Sadachika, T. Murakami, M. Ando, H.J. Mattausch, M. Miura-Mattausch, S. Baba, and J. Ida, "Consistent Dynamic Depletion Model of SOI-MOSFETs for Circuit/Device Optimization", Proceedings of the 34th 2008 IEEE International SOI Conference (SOI'2008), 59-60 (2008)
* K. Okazaki, K. Awane, N. Nagaoka, T. Sugahara, T. Koide, and H.J. Mattausch, "Low-Power Image-Segmentation VLSI Design Based on a Pixel-Block Scanning Architecture", Extended Abstracts of the 2008 International Conference on Solid State Devices and Materials (SSDM'2008), 474-475 (2008)
* M. Miura-Mattausch, M. Yokomichi, N. Sadachika, Y. Oritsuki, T. Sakuda, M. Miyake, T. Kajiwara, H. Kikuchihara, U. Feldmann, and H.J. Mattausch, "Modeling of High-Voltage MOSFETs for Device/Circuit Optimization", Extended Abstracts of the 2008 International Conference on Solid State Devices and Materials (SSDM'2008), 730-731 (2008), Invited Paper
* M. Miyake, D. Hori, N. Sadachika, U. Feldmann, M. Miura-Mattausch, H.J. Mattausch, T. Iizuka, K. Matsuzawa, Y. Sahara, T. Hoshida, and T. Tsukada, "Non-Quasi-Static Carrier Dynamics of MOSFETs under Low-Voltage Operation", Proceedings of the IEEE International Conference on Simulation of Semiconductor Processes and Devices (SISPAD'2008), 381-384 (2008)
* H.J. Mattausch, M. Chan, J. He, H. Koike, M. Miura-Mattausch, T. Nakagawa, Y.J. Park, T. Tsutsumi, and Z. Yu, "Development of Multi-Gate MOSFET Models for Circuit Simulation with a Compact Modeling Platform", Proceedings of the 15th International Conference on Mixed Design of Integrated Circuits and Systems (MIXDES'2008), 59-64 (2008)
* H.J. Mattausch, M. Miura-Mattausch, N. Sadachika, M. Miyake, and D. Navarro, "The HiSIM Compact Model Family for Integrated Devices Containing a Surface-Potential MOSFET Core", Proceedings of the 15th International Conference on Mixed Design of Integrated Circuits and Systems (MIXDES'2008), 39-50 (2008), Invited Plenary Paper
* M. Miyake, A. Ohashi, M. Yokomichi, H. Masuoka, T. Kajiwara, N. Sadachika, U. Feldmann, H.J. Mattausch, M. Miura-Mattausch, T. Kojima, T. Shoji, and Y. Nishibe, "A Consistently Potential Distribution Oriented Compact IGBT Model", Proceedings 39th Annual IEEE Power Electronics Specialists Conference (IEEE PESC' 2008), Island of Rhodes, Greece, June 15-19, 998-1003 (2008)
* Y. Oritsuki, M. Yokomiti, T. Sakuda, N. Sadachika, M. Miyake, T. Kajiwara, U. Feldmann, H.J. Mattausch, and M. Miura-Mattausch, "HiSIM-HV: a complete surface-potential-based MOSFET model for High Voltage Applications", Proceedings of the 2008 NIST Nanotechnology Conference and Trade Show (NIST-Nanotech '2008), 893-896 (2008)
* N. Sadachika, T. Murakami, M. Ando, K. Ishimura, K. Ohyama, M. Miyake, H.J. Mattausch, and M. Miura-Mattausch, "Modeling of Floating-Body Devices Based on Complete Potential Description", Proceedings of the 2008 NIST Nanotechnology Conference and Trade Show (NIST-Nanotech '2008), 778-781 (2008)
* M. Miura-Mattausch, M. Chan, J. He, H. Koike, H.J. Mattausch, T. Nakagawa, Y.J. Park, T. Tsutsumi, and Z. Yu, "Construction of a Compact Modeling Platform and Its Application to the Development of Multi-Gate MOSFET Models for Circuit Simulation", Proceedings of the 2008 NIST Nanotechnology Conference and Trade Show (NIST-Nanotech '2008), 764-769 (2008), Invited Paper
* A. Oohashi, M. Miyake, M. Yokomichi, H. Masuoka, T. Kajiwara, T. Kojima, N. Sadachika, U. Feldmann, H.J. Mattausch, and M. Miura-Mattausch, "High-Voltage MOSFET Model with Consistently Determined Potential Distribution in MOS Channel and Drift Region", Proceedings of the 5th International Workshop on Compact Modeling (IWCM'2008), 49-52 (2008)
* M. Yokomichi, N. Sadachika, M. Miyake, T. Kajiwara, Y. Oritsuki, T. Sakuda, U. Feldmann, H.J. Mattausch, and M. Miura-Mattausch, "High-Voltage MOSFET Model with Consistently Determined Potential Distribution in MOS Channel and Drift Region", Proceedings of the 5th International Workshop on Compact Modeling (IWCM'2008), 49-52 (2008)
* M. Miura-Mattausch, H.J. Mattausch, M. Chan, J. He, H. Koike, T. Nakagawa, Y. J. Park, T. Tutsumi, and Z. Yu, "Construction of a Compact Modeling Platform and its Application to the Development of Multi-Gate MOSFET Models for Circuit Simulation", Proceedings of the 5th International Workshop on Compact Modeling (IWCM'2008), 1-4 (2008), Invited Paper
Publications in 2007
* M. Miura-Mattausch, N. Sadachika, M. Miyake, A. Yumisaki, and H. J. Mattausch, "Analysis of Technology Variations in Advanced MOSFETs with the Surface-Potential-Based Compact Model HiSIM", Electro-Chemical Society (ECS) Transactions, Vol. 11, No. 6, 29-44 (2007)
* K. Johguchi, H.J. Mattausch, T. Koide, and T. Hironaka, "4-Port Unified Data/Instruction Cache Design with Distributed Crossbar and Interleaved Cache-Line Words", IEICE Trans. on Electronics, vol. E90-C, 2157-2160 (2007)
* T. Kumaki, M. Ishizaki, T. Koide, H.J. Mattausch, Y. Kuroda, H. Noda, K. Dosaka, K. Arimoto, and K. Saito, "Acceleration of DCT Processing with Massive-Parallel Memory-Embedded SIMD Matrix Processor", IEICE Trans. on Information & Systems, vol. E90-D, 1312-1315 (2007)
* M.A. Abedin, Y. Tanaka, A. Ahmadi, S. Sakakibara, T. Koide, and H.J. Mattausch, "Realization of K-Nearest-Matches Search Capability in Fully-Parallel Associative Memories", IEICE Trans. on Fundamentals, vol. E90-A, No. 6, 1240-1243 (2007)
* M. Miyake, N. Sadachika, D. Navarro, Y. Mizukane, K. Matsumoto, T. Ezaki, M. Miura-Mattausch, H. J. Mattausch, T. Ohguro, T. Iizuka, M.Taguchi, S. Kumashiro, and S. Miyamoto, "Surface-Potential-Based MOS-Varactor Model for RF Applications", Jpn. J. Appl. Phys., Vol. 46, No. 4B, 2091-2095 (2007)
* M.A. Abedin, Y. Tanaka, A. Ahmadi, T. Koide, and H.J. Mattausch, "Mixed Digital-Analog Associative Memory Enabling Fully-Parallel Nearest Euclidean Distance Search", Jpn. J. Appl. Phys., Vol. 46, No. 4B, 2231-2237 (2007)
* K. Johguchi, Y. Mukuda, K. Aoyama, H.J. Mattausch, and T. Koide, "A 2-stage-pipelined 16 Port SRAM with 590 Gbps Random Access Bandwidth and Large Noise Margin", IEICE Electronics Express, Vol. 4, No. 2, 21-25, (2007)
* T. Kumaki, Y. Kono, M. Ishizaki, T. Koide, and H.J. Mattausch, "Scalable FPGA/ASIC Implementation Architecture for Parallel Table-lookup Coding Using Multi-ported Content Addressable Memory", IEICE Trans. on Information & Systems, vol. E90-D, 346-354 (2007)
* T. Kumaki, Y. Kuroda, M. Ishizaki, T. Koide, H.J. Mattausch, H. Noda, K. Dosaka, K. Arimoto, and K. Saito, "Real-Time Huffman Encoder with Pipelined CAM-Based Data Path and Code-Word-Table Optimizer", IEICE Trans. on Information & Systems, vol. E90-D, 334-345 (2007)
* S. Izumi, K. Johguchi, H.J. Mattausch, and T. Koide, "Static-Noise-Margin Analysis of Major SRAM-Cell Type under Production Variation for a 90nm CMOS Process", 14th Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI'2007), 261-265 (2007)
* Md. Anwarul Abedin, A. Ahmadi, Y. Tanaka, S. Sakakibara, T. Koide, and H.J. Mattausch, "Hardware Realization of Two-Stage Pattern Matching System using Fully-Parallel Associative Memories", 14th Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI'2007), 32-37 (2007)
* T. Kumaki, M. Ishizaki, M. Tagami, T. Koide, and H.J. Mattausch, "An Effective Parallel Coding Architecture Utilizing Characteristics of Multimedia Application", 14th Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI'2007), 74-80 (2007)
* Y. Tanaka, Md. Anwarul Abedin, S. Sakakibara, T. Koide, and H.J. Mattausch, "Area Efficieant Fully Parallel Associative Memory with Fast Winner Search Capability", 14th Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI'2007), 38-41 (2007)
* M. Tagami, M. Ishizaki, T. Kumaki, Y. Kono, T. Koide, H.J. Mattausch, T. Gyohten, H. Noda, K. Dosaka, K. Arimoto, K. Saito, "Acceleration of Advanced Encryption Standard (AES) Processing on a CAM Enhanced Super Parallel SIMD Processor", 14th Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI'2007), 26-31 (2007)
* S. Sakakibara, Md. Anwarul Abedin, Y. Tanaka, A. Ahmadi, H.J. Mattausch, and T. Koide, "Associative Memory Design Realizing Reference-Pattern Recognition and Learning based on Short/Long-Term Storage Concept", 14th Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI'2007), 21-25 (2007)
* K. Okazaki, K. Awane, K. Yamaoka, T. Koide, and H.J. Mattausch, "Performance Evaluation of Region-Growing Image Segmentation Using Two-Dimensional Image-Block Scanning", 14th Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI'2007), 69-73 (2007)
* N. Sadachika, H. Oka, R. Tanabe, T. Murakami, H.J. Mattausch, M. Miura-Mattausch, "Compact Double-Gate MOSFET Model Correctly Predicting Volume-Inversion Effects", Proceedings of the IEEE International Conference on Simulation of Semiconductor Processes and Devices (SISPAD'2007), 289-292 (2007)
* T. Minami, Y. Takeda, M. Miyake,
M. Miura-Mattausch, M. Miura-Mattausch,
H.J. Mattausch, T. Ohguro,
T. Iizuka, M. Taguchi and S. Miyamoto,
"Frequency Dependence of Measured MOSFET Distortion Characteristic",
Extended Abstracts of the 2007 International Conference on
* M. Yokomichi, M. Miyake, T. Kajiwara,
* H.J. Mattausch, M. Miura-Mattausch, N. Sadachika, M. Miyake, T. Iizuka, T. Ohguro, H. Koike, S. Yamaguchi, R. Inagaki, and Y. Furui, "Accuracy and Speed Performance of HiSIM Versions 231 and 240", 33nd European Solid-State Circuits Conference (ESSCIRC'2007), MOS-AK Workshop on Compact Modeling for Nano CMOS/SOI Technologies, Munich, Germany, September 14, (2007)
* K. Johguchi, Y. Mukuda, S. Izumi, H.J. Mattausch, and T. Koide, "A 0.6-Tbps, 16-Port SRAM Design with 2-Stage-Pipeline and Multi-Stage-Sensing Scheme", Proceedings of the 33nd European Solid-State Circuits Conference (ESSCIRC'2007), Munich, Germany, September 11-13, 320-323 (2007)
* T. Kumaki, Y. Kono, M. Ishizaki, M. Tagami, T. Koide, H.J. Mattausch, T. Gyohten, H. Noda, K. Kuroda, K. Dosaka, K. Arimoto, and K. Saito, "CAM Enhanced Super Parallel SIMD Processor with High-Speed Pattern Matching Capability", Proceedings of the 50th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS'2007), 803-806 (2007)
* Y. Furui, M. Miura-Mattausch, N. Sadachika, M. Miyake, T. Ezaki, H.J. Mattausch, T. Ohguro, T. Iizuka, R. Inagaki, and N. Fudanuki, "STARC's Semiconductor Design Technology Research Activities and the HiSIM2 Advanced MOSFET Model Project", Proceedings of the 14th International Conference on Mixed Design of Integrated Circuits and Systems (MIXDES'2007), 41-46 (2007), Invited Keynote Paper
* M. Miura-Mattausch, N. Sadachika, M. Miyake, D. Navarro, T. Ezaki, H.J. Mattausch, T. Ohguro, T. Iizuka, M. Taguchi, S. Miyamoto, R. Inagaki, Y. Furui, N. Fudanuki, and T. Yoshida, "HiSIM2.4.0: Advanced MOSFET Model for the 45nm Technology Node and Beyond", Proceedings of the 2007 NIST Nanotechnology Conference and Trade Show (NIST-Nanotech '2007), 479-484 (2007), Invited Paper
* M. Miyake, N. Sadachika, K. Matsumoto, D. Navarro, T. Ezaki, M. Miura-Mattausch, H. J. Mattausch, T. Ohguro, T. Iizuka, M. Taguchi, and S. Miyamoto, "HiSIM-Varactor: Complete Surface-Potential-Based Model for RF Applications", Proceedings of the 2007 NIST Nanotechnology Conference and Trade Show (NIST-Nanotech '2007), 621-624 (2007)
* T. Kumaki, T. Koide, H.J. Mattausch, Y. Kuroda, H. Noda, K. Dosaka, K. Arimoto, and K. Saito "Efficient Vertical/Horizontal-Space 1D-DCT Processing Based on Massive-Parallel Matrix-Processing Engine", Proc. IEEE Int. Symposium on Circuits and Systems (ISCAS'07), 525-528 (2007)
* A. Ahmadi, H.J. Mattausch, M. A. Abedin, T. Koide, Y. Shirakawa, and M. A. Ritonga, "Developing a Reliable Learning Model for Cognitive Classification Tasks Using an Associative Memory", Proceedings of the 2007 IEEE Symposium on Computational Intelligence in Image and Signal Processing (CIISP'2007), 214-219 (2007)
* H.J. Mattausch, N. Sadachika, M. Miyake, D. Navarro, T. Warabino, K. Matsumoto, T. Ezaki, M. Miura-Mattausch, T. Yoshida, R. Inagaki, Y. Furui, S. Hazama, T. Ohguro, T. Iizuka, M. Taguchi, S. Kumashiro, and S. Miyamoto, "HiSIM231: Toward Solving the Speed versus Accuracy Crisis in Circuit Simulation", Proceedings of the 4th International Workshop on Compact Modeling (IWCM'2007), 93-96 (2007)
Publications in 2006
* H. Noda, K. Dosaka, H.J. Mattausch, T. Koide, F. Morishita, and K. Arimoto, "A Reliability-Enhanced TCAM Architecture with Associated Embedded DRAM and ECC", IEICE Trans. on Electronics, vol. E89-C, 1612-1619 (2006)
* K. Tanigawa, T. Hironaka, M. Maeda, T. Sueyoshi, K. Aoyama, T. Koide and H.J. Mattausch, "Performance Evaluation of Superscalar Processor with Multi-Bank Register File and an Implementation Result," WSEAS Transactions on Computer, Issue 9, Vol. 5, 1993-2000 (2006)
* H.J. Mattausch,
M. Miyake, T. Yoshida,
* N. Sadachika, D. Kitamaru, Y. Uetsuji, D. Navarro, M. M. Yusoff, T. Ezaki, H.J. Mattausch, and M. Miura-Mattausch, "Completely Surface-Potential-Based Compact Model of the Fully-Depleted SOI-MOSFET Including Short-Channel Effects", IEEE Trans. on Electron Devices 53, No. 9, 2017-2024 (2006)
* D. Navarro, Y. Takeda, M. Miyake, N. Nakayama, K. Machida, T. Ezaki, H.J. Mattausch, and M. Miura-Mattausch, "A Carrier-Transit-Delay-Based Non-Quasi-Static MOSFET Model for Circuit Simulation and Its Application to Harmonic Distortion Analysis", IEEE Trans. on Electron Devices 53, No. 9, 2025-2034 (2006)
* M. Miura-Mattausch, N. Sadachika, D. Navarro, G. Suzuki, Y. Takeda, M. Miyake, T. Warabino, Y. Mizukane, K. Machida, R. Inagaki, T. Ezaki, H.J. Mattausch, T. Ohguro, T. Iizuka, M. Taguchi, S. Kumashiro and S. Miyamoto, "HiSIM2: Advanced MOSFET Model Valid for RF-Circuit Simulation", IEEE Trans. on Electron Devices 53, No. 9, 1994-2007 (2006)
* D. Navarro, Y. Takeda, M. Miura-Mattausch, H.J. Mattausch, T. Ohguro, T. Iizuka, M. Taguchi, S. Kumashiro and S. Miyamoto, "On the Validity of Conventional MOSFET Nonlinearity Characterization at RF Switching", IEEE Microwave and Wireless Components Letters Vol. 16 Nr. 3, 125-127 (2006)
* T. Morimoto, H. Adachi, O. Kiriyama, T. Koide, and H.J. Mattausch, "Boundary-Active-Only Adaptive Power-Reduction Scheme for Region-Growing Video Segmentation", IEICE Trans. on Information & Systems, vol. E89-D, 1299-1302 (2006)
* Tomohiro Inoue, Tetsuo Hironaka, Takahiro Sasaki, Seiji Fukae, Tetsushi Koide and H. J. Mattausch, "Evaluation of Bank based Multi-port Memory Architecture with Blocking Network," Wiley, Systems & Computers in Japan, Vol.37, No.2, 22-33, (2006)
* T. Ezaki, G. Suzuki, K. Konno, O. Matsushima, Y. Mizukane, D. Navarro, M. Miyake, N. Sadachika, H.J. Mattausch, and M. Miura-Mattausch, "Physics-Based Photodiode Model Enabling Consistent Opto-Electronic Circuit Simulation", Proceedings of the 2006 IEEE International Electron Devices Meeting (IEDM'2006), 187-190 (2006)
* Y. Mukuda, K. Aoyama, K. Johguchi, H.J. Mattausch, T. Koide, M. Maeda, T. Hironaka, and K. Tanigawa, "Access Queues for Multi-Bank Register Files Enabling Enhanced Performance of Highly Parallel Processors", Proc. of the IEEE TENCON (TENCON'2006), No. CA2.4 (2006)
* M. Ishizaki, T. Kumaki, Y. Kouno, T. Koide, H.J. Mattausch, Y. Kuroda, T. Gyoten, H. Noda, K. Dosaka, K. Arimoto and K. Saito, "Huffman Encoding Architecture with Self-Optimizing Performance and Multiple CAM-Match Utilization", Proc. of the IEEE TENCON (TENCON'2006), No. CA2.3 (2006)
* K. Johguchi, Z. Zhu, H.J. Mattausch, T. Koide, T. Hironaka, and K. Tanigawa, "Unified Data/Instruction Cache with Hierarchical Multi-Port Architecture and Hidden Precharge Pipeline", Proc. of the IEEE Asia Pacific Conference on Circuits and Systems (APCCAS'2006), 1299-1302 (2006)
* T. Kumaki, Y. Kouno, M. Ishizaki, T. Koide, H.J. Mattausch, "Application of Multi-ported CAM for Parallel Coding", Proc. of the IEEE Asia Pacific Conference on Circuits and Systems (APCCAS'2006), 1681-1684 (2006)
* T. Morimoto, H. Adachi, K. Yamaoka, T. Koide and H.J. Mattausch, "An FPGA-Based Region-Growing Video Segmentation System with Boundary-Scan-Only LSI Architecture", Proc. of the IEEE Asia Pacific Conference on Circuits and Systems (APCCAS'2006), 946-949 (2006)
* Md. A. Abedin, Y. Tanaka, A. Ahmadi, T. Koide and H.J. Mattausch, "Fully Parallel Associative Memory Architecture with Mixed Digital-Analog Match Circuit for Nearest Euclidean Distance Search", Proc. of the IEEE Asia Pacific Conference on Circuits and Systems (APCCAS'2006), 1311-1314 (2006)
* T. Ezaki, T. Warabino, M. Miyake, N. Sadachika, D. Navarro, H.J. Mattausch, M. Miura-Mattausch, T. Ohguro, T. Iizuka, M. Taguchi, S. Kumashiro, and S. Miyamoto, "Noise Modeling Based on Self-Consistent Surface-Potential Description for Advanced MOSFETs aiming at RF Applications", Proceedings of the 8th International Conference on Solid-State and Integrated-Circuit Technology (ICSICT'2006), 1264-1267 (2006), Invited Paper
* N. Sadachika, D. Kitamaru, Y. Uetsuji, D. Navarro, M. M. Yusoff, T. Ezaki, H.J. Mattausch, M. Miura-Mattausch, and S. Baba, "HiSIM-SOI: Complete Surface-Potential-Based Fully-Depleted SOI-MOSFET Model for Circuit Simulation", Proc. 2006 China-Ireland International Conference on Information and Communication Technologies (CIICT'2006), 242-245 (2006)
* M. Miyake, N. Sadachika, D. Navarro, Y. Mizukane, T. Ezaki, M. Miura-Mattausch, H.J. Mattausch, T. Ohguro, T. Iizuka, M. Taguchi, S. Kumashiro, and S. Miyamoto, "Surface-Potential-Based MOS-Varactor Model for RF Applications", Extended Abstracts of the 2006 International Conference on Solid State Devices and Materials (SSDM'2006), 1044-1045 (2006)
* T. Morimoto, H. Adachi, K. Yamaoka, K. Awane, T. Koide and H.J. Mattausch, "Image-Scan Video Segmentation Architecture and FPGA Implementation", Extended Abstracts of the 2006 International Conference on Solid State Devices and Materials (SSDM'2006), 590-591 (2006)
* Md. A. Abedin, Y. Tanaka, A. Ahmadi, T. Koide and H.J. Mattausch, "Nearest Euclidean-Distance-Search Associative Memory Architecture with Fully Parallel Mixed Digital-Analog Match Circuitry", Extended Abstracts of the 2006 International Conference on Solid State Devices and Materials (SSDM'2006), 282-283 (2006)
* K. Johguchi, K. Aoyama, T. Sueyoshi, H.J. Mattausch, T. Koide, M. Maeda, T. Hironaka, and K. Tanigawa, " Multi-Bank Register File for Increased Performance of Highly-Parallel Processors", Proceedings of the 32nd European Solid-State Circuits Conference (ESSCIRC'2006), Montreux, Switzerland, September 18-22, 154-157 (2006)
* T. Warabino, M. Miyake, N. Sadachika, D. Navarro, Y. Takeda, G. Suzuki, T. Ezaki, M. Miura-Mattausch, H.J. Mattausch, T. Ohguro, T. Iizuka, M. Taguchi, S. Kumashiro, and S. Miyamoto, "Analysis and Compact Modeling of MOSFET High-Frequency Noise", Proceedings of the IEEE International Conference on Simulation of Semiconductor Processes and Devices (SISPAD'2006), 158-161 (2006)
* K. Tanigawa, T. Hironaka, M. Maeda, T. Sueyoshi, K. Aoyama, T. Koide and H.J. Mattausch, "Performance Evaluation of Superscalar Processor with Multi-Bank Register File Using SPEC2000," Proceedings of the 10th WSEAS International Conference on COMPUTERS, 1062-1067, (2006)
* A. Ahmadi, M. A. Ritonga, Md. A. Abedin, H.J. Mattausch, and T. Koide, "A Learning OCR System Using Short/Long-term Memory Approach and Hardware Implementation in FPGA", Proceedings of the 2006 IEEE Congress on Evolutionary Computation (WCCI'2006), 2702-2708 (2006)
* M. Miura-Mattausch, D. Navarro, N. Sadachika, G. Suzuki, Y. Takeda, M. Miyake, T. Warabino, K. Machida, T. Ezaki, H.J. Mattausch, T. Ohguro, T. Iizuka, M. Taguchi, S. Kumashiro, R. Inagaki, and S. Miyamoto, "Advanced Compact MOSFET Model HiSIM2 Based on Surface Potentials with a Minimum Number of Approximations", Proceedings of the 2006 NIST Nanotechnology Conference and Trade Show (NIST-Nanotech '2006), 638-643 (2006), Invited Paper
* Md. A. Abedin, K. Kamimura, A. Ahmadi, T. Koide and H.J. Mattausch, "Minimum Euclidean Distance Associative Memory Architecture with Fully-Parallel Search Capability", 13th Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI'2006), 350-354 (2006)
*K. Yamaoka, T. Morimoto, H. Adachi, K. Awane, T. Koide, and H.J. Mattausch, "Multi-Object Tracking VLSI Architecture using Image-Scan based Region Growing and Feature Matching", Proc. IEEE Int. Symposium on Circuits and Systems (ISCAS'06), 5575-5578 (2006)
* K. Machida, D. Navarro, M. Miyake, R. Inagaki, N. Sadachika, T. Ezaki, H.J. Mattausch, and M. Miura-Mattausch, "Efficient non-quasi-static MOSFET Model for both Time-Domain and Frequency-Domain Analysis", Proceedings of the IEEE International Conference on Silicon Monolithic Integrated Circuits in RF Systems (SiRF'06), 73-76 (2006)
* M. Miura-Mattausch, D. Navarro, N. Sadachika, G. Suzuki, Y. Takeda, M. Miyake, T. Warabino, Y. Mizukane, K. Machida, R. Inagaki, T. Ezaki, H.J. Mattausch, T. Ohguro, T. Iizuka, M. Taguchi, S. Kumashiro, and S. Miyamoto, "HiSIM2: Advanced MOSFET Model for RF-Circuit Simulation", Proceedings of the 3rd International Workshop on Compact Modeling (IWCM'2006), 57-62 (2006)
* K. Yamaoka, T. Morimoto, H. Adachi, T. Koide, and H.J. Mattausch, "Image Segmentation and Pattern Matching Based FPGA/ASIC Implementation of Real-Time Object Tracking", Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC'2006), 176-181 (2006)
Publications in 2005
* T. Morimoto, Y. Harada, T. Koide, H.J. Mattausch, "Pixel-Parallel Digital-CMOS Implementation of Image-Segmentation by Region Growing", IEE Proc. Circuits, Devices & Systems , 579-589 (2005)
* S. Hosokawa, D. Navarro, M. Miura-Mattausch, H.J. Mattausch, T. Ohguro, T. Iizuka, M. Taguchi, S. Kumashiro and S. Miyamoto, "Gate-length and drain-voltage dependence of thermal drain noise in advanced metal-oxide-semiconductor-field-effect transistors", Appl. Phys. Lett. 87, 092104 (2005)
* T. Inoue, T. Hironaka, T. Sasaki, S. Fukae, T. Koide, and H.J. Mattausch, "Evaluation of a Bank-based Multi-port Memory Architecture with Blocking Network", "閉塞網を用いたオンチップバンク型多ポートメモリの検討と回路規模評価", IEICE Trans. on Fundamentals of Electronics, Communications and Computer Science, vol. J87-A, 498-510 (2005) (in Japanese)
* K. Inoue, H. Noda, K. Arimoto, H.J. Mattausch, and T. Koide, "A CAM-based signature-matching co-processor with application-driven power-reduction features", IEICE Trans. on Electronics, vol. E88-C, 1332-1342 (2005)
* D. Navarro, T. Mizoguchi, M. Suetake, K. Hisamitsu, H. Ueno, M. Miura-Mattausch, H.J. Mattausch, S. Kumashiro, T. Yamaguchi, K. Yamashita and N. Nakayama, "A Compact Model of the Pinch-Off Region of 100nm MOSFETs Based on the Surface Potential", IEICE Trans. on Electronics, vol. E88-C, 1079-1086 (2005)
* H. Noda, K. Inoue, H.J. Mattausch, T. Koide, K. Dosaka, K. Arimoto, K. Fujishima, K. Anami, and T. Yoshihara, "Embedded Low-Power Dynamic TCAM Architecture with Transparently Scheduled Refresh", IEICE Trans. on Electronics, vol. E88-C, 622-629 (2005)
* S. Matsumoto, H. Ueno, S. Hosokawa, T. Kitamura, M. Miura-Mattausch, H.J. Mattausch, T. Ohguro, S. Kumashiro, T. Yamaguchi, K. Yamashita, and N. Nakayama, "1/f-Noise Characteristics in 100nm MOSFETs and Its Modeling for Circuit Simulation", IEICE Trans. on Electronics, vol. E88-C, 247-254 (2005)
* H. Noda, K. Inoue, M. Kuroiwa, F. Igaue, K. Yamamoto, H.J. Mattausch, T. Koide, A. Amo, A. Hachisuka, S. Soeda, F. Morishita, K. Dosaka, K. Arimoto, and T. Yoshihara, "A Cost-Efficient High-Performance Dynamic TCAM with Pipelined Hierarchical Searching and Shift Redundancy Architecture", IEEE Journal of Solid-State Circuits, 40, 245-253 (2005)
* T. Sasaki, T. Inoue, N, Omori, T. Hironaka, H.J. Mattausch, and T. Koide, "Chip Size and Performance Evaluations of Shared Cache for On-chip Multiprocessors", Systems & Computers in Japan No.36(9), 1-13 (2005)
* Y. Kuroda, T. Kumaki, T. Koide, H.J. Mattausch, H. Noda, K. Dosaka, K. Arimoto, and K. Saito, "Highly Parallel Huffman Encoding by Exploiting Multiple Matches in Content Addressable Memory", Proceedings of the International SoC Design Conference (ISOCC'2005), 313-316 (2005)
* H. Adachi, T. Morimoto, K. Yamaoka, T. Koide, and H.J. Mattausch, "Image-Scan Architecture for Efficient FPGA/ASIC Implementation of Video-Segmentation by Region Growing", Proceedings of the International SoC Design Conference (ISOCC'2005), 301-304 (2005)
* A. Ahmadi, Md. A. Abedin, H.J. Mattausch, and T. Koide, "A Parallel Hardware Design for Parametric Active Contour Models", Proceedings of the IEEE International Conference on Advanced Video and Signal based Surveillance (AVSS'2005), 609-613 (2005)
* A. Ahmadi, Y. Shirakawa, Md. A. Abedin, K. Kamimura, H.J. Mattausch, and T. Koide, "An LSI hardware design for online character recognition using associative memory", Proceedings of the 48th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS'2005), 464-467 (2005)
* T. Kumaki, Y. Kuroda, T. Koide, H.J. Mattausch, H. Noda, K. Dosaka, K. Arimoto, and K. Saito, "Multi-Port CAM based VLSI Architecture for Huffman Coding with Real-time Optimized Code Word Table", Proceedings of the 48th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS'2005), 55-58 (2005)
* Y. Takeda, D. Navarro, S. Chiba, M. Miura-Mattausch, H.J. Mattausch, T. Ohguro, T. Iizuka, M. Taguchi, S. Kumashiro and S. Miyamoto, "MOSFET Harmonic Distortion Analysis up to the Non-Quasi-Static Frequency Regime", Proceedings of the IEEE Custom Integrated Circuits Conference (CICC'2005), 827-830 (2005)
* A. Ahmadi, H.J. Mattausch, and T. Koide, "A Parallel Hardware Design for Snake Models with an FPGA Architecture", International Workshop on Nonlinear Signal and Image Processing (NSIP'2005), 146-150 (2005)
* T. Kumaki, Y. Kuroda, T. Koide, H.J. Mattausch, H. Noda, K. Dosaka, K. Arimoto, and K. Saito, "CAM-based VLSI Architecture for Huffman Coding with Real-time Optimization of the Code Word Table", Proc. IEEE Int. Symposium on Circuits and Systems (ISCAS'05), Kobe 2005, 5202-5205 (2005)
* T. Morimoto, O. Kiriyama, Y. Harada, H. Adachi, T. Koide, and H.J. Mattausch, "Object Tracking in Video Pictures based on Image Segmentation and Pattern Matching", Proc. IEEE Int. Symposium on Circuits and Systems (ISCAS'05), Kobe 2005, 3215-3218 (2005)
* T. Saito, M. Maeda, T. Hironaka, K. Tanigawa, T. Sueyoshi, K. Aoyama, T. Koide, and H.J. Mattausch, "Design of Superscalar Processor with Multi-Bank Register File", Proc. IEEE Int. Symposium on Circuits and Systems (ISCAS'05), Kobe 2005, 3507-3510 (2005)
* T. Morimoto, O. Kiriyama, H. Adachi, Z. Zhu, T. Koide, and H.J. Mattausch, "A Low-Power Video Segmentation LSI with Boundary-Active-Only Architecture", Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC'2005.1), D13-D14 (2005), Best Design Award
Publications in 2004
* M. Miura-Mattausch, H.J. Mattausch, T. Ohguro, T. Iizuka, M. Taguchi, S. Kumashiro and S. Miyamoto, "MOSFET Model HiSIM Based on Surface-Potential Description for Enabling Accurate RF-CMOS Design", Journal of Semiconductor Technology and Science Vol. 4 No.3, 133-140 (2004)
* N. Nakayama, D. Navarro, M. Tanaka, H. Ueno, M. Miura-Mattausch, H.J. Mattausch, T. Ohguro, S. Kumashiro, T. Yamaguchi, M. Taguchi and S. Miyamoto, "Non-quasi-static model for MOSFET based on carrier-transit delay", IEE Electronics Letters 40, 276-278 (2004)
* K. Johguchi, Z. Zhu, T. Hirakawa, T. Koide, T. Hironaka, and H.J. Mattausch, "Distributed-crossbar architecture for area-efficient combined data/instruction caches with multiple ports", IEE Electronics Letters 40, 160-162 (2004)
* S. Fukae, T. Inoue, H.J. Mattausch, T. Koide, and T. Hironaka, "Distributed against centralized crossbar function for realizing bank-based multiport memories", IEE Electronics Letters 40, 101-103 (2004)
* T. Morimoto, Y. Harada, T. Koide, and H.J. Mattausch, "Efficient Video-Picture Segmentation Algorithm for Cell-Network-Based Digital CMOS Implementation", IEICE Trans. on Information & Systems, vol. E87-D, 500-503 (2004)
* T. Sasaki, T. Inoue, N, Omori, T. Hironaka, H.J. Mattausch, and T. Koide, "Chip Size and Performance Evaluations of Shared Cache for On-chip Multiprocessors", "オンチップ・マルチプロセッサ用共有キャッシュの実現方式の検討とその性能面積評価", IEICE Trans. on Information & Systems Part 1, vol. J87-D-I, 350-363 (2004) (in Japanese)
* A. Ahmadi, H.J. Mattausch, T. Koide, "A Numerical Approach for Snake Models and Implementation with an FPGA Architecture", Proceedings of the Annual Workshop on Circuits, Systems and Signal Processing (ProRISC'2004), 1-6 (2004)
* M. Miura-Mattausch,
H.J. Mattausch, T. Ohguro,
T. Iizuka, M. Taguchi,
* H. Adachi, T. Morimoto, O. Kiriyama, T. Koide and H.J. Mattausch, "Real-Time Segmentation of Large-Scale Images by Pipeline Processing with Small-Size Cell Network", 12th Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI'2004), 95-102 (2004)
* T. Fuji, K. Kobayashi, T. Koide, H.J. Mattausch and T. Hironaka, "Highly Efficient Switch Architecture Based on Banked Memory with Multiple Ports", 12th Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI'2004), 491-498 (2004)
* N. Sadachika, Y. Uetsuji, D. Kitamaru, L. Weiss, U. Feldmann, S. Baba, H.J. Mattausch and M. Miura-Mattausch, "Fully-Depleted SOI-MOSFET Model for Circuit Simulation and its Application to 1/f Noise Analysis", Proceedings of the IEEE International Conference on Simulation of Semiconductor Processes and Devices (SISPAD'2004), 255-258 (2004)
* D. Navarro, N. Nakayama, K. Machida, Y. Takeda, H. Ueno, H.J. Mattausch, M. Miura-Mattausch, T. Ohguro, T. Iizuka, M. Taguchi, T. Kage and S. Miyamoto, "Modeling of Carrier Transport Dynamics at GHz-Frequencies for RF Circuit Simulation", Proceedings of the IEEE International Conference on Simulation of Semiconductor Processes and Devices (SISPAD'2004), 259-262 (2004)
* T. Koide, Y. Yano and H.J. Mattausch, "Bank-Type Associative Memory for
High-Speed Nearest
* Y. Shirakawa,
M. Mizokami, T. Koide and H.J. Mattausch,
"Automatic Pattern-Learning Architecture Based on Associative Memory and
Short/Long Term Storage Concept", Extended Abstracts of the 2004
International Conference on
* T. Morimoto, O. Kiriyama, H. Adachi, T. Koide and H.J. Mattausch, "Digital Low-Power Real-Time Video
Segmentation by Region Growing", Extended Abstracts of the 2004
International Conference on
* M. Miura-Mattausch, D. Navarro, Y. Takeda, H.J. Mattausch, T. Ohguro, T. Iizuka, M. Taguchi and S. Miyamoto, "MOSFET Modeling for RF-Circuit Era", Proceedings of the 11th International Conference on Mixed Design (MIXDES'2004), 62-66 (2004), Invited Paper
* K. Takemura, T. Koide, H.J. Mattausch, and T. Tsuji, "Analog-Circuit-Component Optimization with Genetic Algorithm", Proceedings of the 47th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS'2004) Vol. I, 489-492 (2004)
* K. Kamimura,
K. M. Rahman, H.J. Mattausch,
and T. Koide, "Optimized Multi-Stage Minimum-Distance-Search Circuit with
Feedback Stabilization for Fully-Parallel Associative Memories",
Proceedings of the 47th IEEE International
* Y. Shirakawa, H.J. Mattausch, and T. Koide, "Reference-Pattern Learning and Optimization from an Input-Pattern Stream for Associative-Memory-Based Pattern-Recognition System", Proceedings of the 47th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS'2004) Vol. I, 561-564 (2004)
* Z. Zhu, K. Johguchi, H.J. Mattausch, T. Koide, and T. Hironaka, "Low Power Bank-based Multi-port SRAM Design due to Bank Standby Mode", Proceedings of the 47th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS'2004) Vol. I, 569-572 (2004)
* O. Kiriyama, T. Morimoto, H. Adachi, Y. Harada, T. Koide and H.J. Mattausch, "Low-Power Design for Real-Time Image Segmentation LSI and Compact Digital CMOS Implementation", Proceedings of the 2004 IEEE Asia-Pacific Conference on ASICs (AP-ASIC'2004), 432-433 (2004)
* T. Inoue, T. Hironaka, T. Sasaki, S. Fukae, T. Koide, H.J. Mattausch, "Proposition and Evaluation of a Bank-Based Multi-Port Memory with Blocking Network", Proceedings of the 2004 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC'2004), 6C2L-3 (2004)
* M. Miura-Mattausch, S. Matsumoto, K. Mizoguchi, D. Miyawaki, H.J. Mattausch, S. Itoh, and K. Morikawa, "Test Circuits for Extracting Sub-100nm MOSFET Technology Variations with the MOSFET Model HiSIM", Proceedings of the IEEE International Conference on Microelectronic Test Structures (ICMTS'2004), 267-272 (2004), Invited Paper
* M. Miura-Mattausch, S. Hosokawa, D. Navarro, S. Matsumoto, H. Ueno, H.J. Mattausch, T. Oguro, T. Iizuka, M. Taguchi, T. Kage, and S. Miyamoto, "Noise Modeling with HiSIM Based on Self-Consistent Surface-Potential Description", Proceedings of the 2004 NIST Nanotechnology Conference and Trade Show (NIST-Nanotech'2004), 66-69 (2004), Invited Paper
* H. Noda, K. Inoue, M. Kuroiwa, A. Amo, A. Hachisuka, H.J. Mattausch, T. Koide, S. Soeda, K. Dosaka, and K. Arimoto, "A 143MHz, 1.1W, 4.5Mb dynamic TCAM with hierarchical searching and shift redundancy architecture", IEEE International Solid-State Circuits Conference Digest of Tech. Papers (ISSCC'2004), 208-209 (2004)
* Y. Yano, T. Koide, and H.J. Mattausch, "Associative Memory with Fully Parallel
Nearest-Manhattan-Distance Search for Low-Power Real-Time Single-Chip
Applications", Proceedings of the
* T. Sueyoshi, H. Uchida, Y. Mitani, K. Hiramatsu, H.J. Mattausch, T. Koide, and T. Hironaka, "Compact 12-Port Multi-Bank Register File Test Chip in 0.35mm CMOS for Highly Parallel Processors", Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC'2004), 551-552 (2004)
* T. Morimoto, Y. Harada T. Koide,
and H.J. Mattausch, "350nm CMOS Test-Chip
for Architecture Verification of Real-Time QVGA Color-Video Segmentation at the
90nm Technology Node", Proceedings of the
Publications in 2003
* D. Navarro, H. Kawano, K. Hisamitsu, T. Yamaoka, M. Tanaka, H. Ueno, M. Miura-Mattausch, H.J. Mattausch, S. Kumashiro, T. Yamaguchi, K. Yamashita and N. Nakayama, "Circuit-Simulation Model of Cgd Changes in Small-Size MOSFETs Due to High Channel-Field Gradients", IEICE Trans. on Electronics, vol. E86-C, 474-480 (2003)
* M. Miura-Mattausch, H. Ueno, H.J. Mattausch, K. Morikawa, S. Itoh, A. Kobayashi, and H. Masuda, "100nm-MOSFET Model for Circuit Simulation: Challenges and Solutions", IEICE Trans. on Electronics, vol. E86-C, 1009-1021 (2003), Invited Paper
* T. Koide, H.J. Mattausch, Y. Yano, T. Gyohten and Y. Soda, "A Nearest-Hamming-Distance Search Memory with Fully Parallel Mixed Digital-Analog Match Circuitry", Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC'2003), 591-592 (2003), Special Feature Award, University Design Contest
* K. Hisamitsu, H. Ueno, M. Tanaka, D. Kitamaru, M. Miura-Mattausch, H. J. Mattausch, S. Kumashiro, T. Yamaguchi, K. Yamashita and N. Nakayama, "Temperature-Independence-Point Properties for 0.1mm-Scale Pocket-Implant Technologies and the Impact on Circuit Design", Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC'2003), 179-183 (2003)
* T. Koide, Y. Yano, H. J. Mattausch, "An Associative Memory for Real-Time Applications Requiring Fully-Parallel Nearest Manhattan-Distance Search", 11th Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI'2003), 200-205 (2003)
* S. Fukae,
* Z. Zhu, K. Johguchi, H.J. Mattausch, T. Koide, T. Hirakawa and T. Hironaka, "High Access Bandwidth Multi-Port-Cache Design with Compact Hierarchical 1-Port-Bank Structure", 11th Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI'2003), 394-400 (2003)
* T. Mizoguchi, H. Ueno, H.J. Mattausch, D. Kitamaru, K. Hisamitsu, M. Miura-Mattausch and S. Itoh, "Extraction of Inter- and Intra-Chip Device-Parameter Variations with a Differential-Amplifier Stage Test Circuit", 11th Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI'2003), 76-82 (2003)
* Z. Zhu, K. Johguchi, H.J. Mattausch, T. Koide, T. Hirakawa and T. Hironaka, "High-Speed and Low-Power Multi-Port-Cache", Proceedings of COOL Chips VI, 76 (2003)
* H. Noda, K. Inoue, H.J. Mattausch, T. Koide and K. Arimoto, "A Cost-Efficient Dynamic Ternary CAM in 130nm CMOS Technology with Planar Complementary Capacitors and TSR Architecture", 2003 Symposium on VLSI Circuits Digest of Technical Papers, 83-84 (2003)
* Y. Harada, T. Morimoto, T. Koide, H.J. Mattausch, "CMOS Test Chip for a High-Speed Digital Image-Segmentation Architecture with Pixel-Parallel Processing", Proceedings of the 2003 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC'2003), 284-287 (2003)
* Z. Zhu, K. Johguchi,
H.J. Mattausch, T. Koide, T. Hirakawa and T. Hironaka, "A
Novel Hierarchical Multi-Port Cache", Proceedings of the 29th European
Solid-State Circuits Conference (ESSCIRC'2003),
* T. Morimoto, Y. Harada, T. Koide
and H.J. Mattausch, "Low-Power Real-Time
Region-Growing Image-Segmentation in 0.35mm CMOS due to Subdivided-Image and
Boundary-Active-Only Architectures", Extended Abstracts of the 2003
International Conference on
* T. Sueyoshi,
H. Uchida, Y. Mitani, K. Hiramatsu,
H.J. Mattausch, T. Koide, and T. Hironaka, "Bank-Type Multiport Register File for
Highly-Parallel Processors", Extended Abstracts of the 2003 International
Conference on
* K. Johguchi,
Z. Zhu, T. Hirakawa, T. Koide, T. Hironaka,
and H.J. Mattausch, "Combined
Data/Instruction Cache with Bank-Based Multi-Port Architecture", Extended
Abstracts of the 2003 International Conference on
* S. Fukae,
* S. Hosokawa, Y. Shiraga, H. Ueno, M. Miura-Mattausch,
H.J. Mattausch, T. Ohguro,
Publications in 2002
* S. Matsumoto, H. Ueno, M. Miura-Mattausch, H.J. Mattausch, S. Kumashiro, T. Yamaguchi, K. Yamashita, and N. Nakayama, "Validity of the mobility universality for scaled MOSFETs down to 100nm gate length", J. Appl. Phys. 92, 5228-5232 (2002)
* H. Ueno, D. Kitamaru, K. Morikawa, M. Tanaka, M. Miura-Mattausch, H.J. Mattausch, S. Kumashiro, T. Yamaguchi, K. Yamashita, and N. Nakayama, "Impurity-Profile-Based Threshold-Voltage Model of Pocket-Implanted MOSFETs for Circuit Simulation", IEEE Trans. on Electron Devices 49, 1783-1789 (2002)
* H. J. Mattausch, M. Suetake, D. Kitamaru, M. Miura-Mattausch, S. Kumashiro, N. Shigyo, S. Odanaka and N. Nakayama, "Simple nondestructive extraction of the vertical channel-impurity profile of small-size metal-oxide-semiconductor-field-effect transistors", Appl. Phys. Lett. 80, 2994-2996 (2002)
* K. Morikawa, H. Ueno, D. Kitamaru, M. Tanaka, T. Okagaki, M. Miura-Mattausch, H.J. Mattausch, S, Kumashiro, T. Yamaguchi, K. Yamashita and N. Nakayama, "Quantum Effect in Sub-100nm MOSFET with Pocket Technologies and its Relevance for the On-Current Condition", Jpn. J. Appl. Phys. 41, 2359-2362 (2002)
* M. Miura-Mattausch, H. Ueno, H.J. Mattausch, S. Kumashiro, T. Yamaguchi, K. Yamashita, and N. Nakayama, "Circuit Simulation Models for Coming MOSFET Generations", IEICE Trans. Fundamentals, vol. E85-A, no. 4, 740-748 (2002)
* H.J. Mattausch, T. Gyohten, Y. Soda and T. Koide, "Compact Associative-Memory Architecture with Fully-Parallel Search Capability for the Minimum Hamming Distance", IEEE Journal of Solid-State Circuits, 37, 218-227, (2002)
* M. Miura-Mattausch, H. Ueno, M. Tanaka, H.J. Mattausch, S. Kumashiro, T. Yamaguchi, K. Yamashita and N. Nakayama, "HiSIM: A MOSFET Model for Circuit Simulation Connecting Circuit Performance with Technology", Proceedings of the 2002 IEEE International Electron Devices Meeting (IEDM'2002), 109-112 (2002), Invited Paper
* S. Jinbou, H. Ueno, H. Kawano, K. Morikawa, N. Nakayama, M. Miura-Mattausch and H.J. Mattausch, "Analysis of Non-Quasistatic Contribution to Small-Signal Response for Deep Sub-Micron MOSFET Technologies", Extended Abstracts of the 2002 International Conference on Solid State Devices and Materials (SSDM'2002), 26-27 (2002)
* Y. Yano, T. Koide and H.J. Mattausch, "Fully Parallel Nearest Manhattan-Distance-Search Memory with Large Reference-Pattern Number", Extended Abstracts of the 2002 International Conference on Solid State Devices and Materials (SSDM'2002), 254-255 (2002)
* T. Morimoto, Y. Harada, T. Koide and H.J. Mattausch, "Low-Complexity, Highly-Parallel Color Motion-Picture Segmentation Architecture for Compact Digital CMOS Implementation", Extended Abstracts of the 2002 International Conference on Solid State Devices and Materials (SSDM'2002), 242-243 (2002)
* T. Morimoto, Y. Harada, T. Koide and H.J. Mattausch, "Real-Time Segmentation Architecture of Gray-Scale/Color Motion Pictures and Digital Test-Chip Implementation", Proceedings of the 2002 IEEE Asia-Pacific Conference on ASICs (AP-ASIC'2002), 237-240 (2002)
* T. Koide, T. Morimoto, Y. Harada, H.J. Mattausch, "Digital Gray-Scale/Color Image-Segmentation Architecture for Cell-Network-Based Real-Time Applications", Proceedings of the 2002 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC'2002), 670-673 (2002)
* H. Ueno, S. Jinbou, H. Kawano, K. Morikawa, N. Nakayama, M. Miura-Mattausch and H.J. Mattausch, "Drift-Diffusion-Based Modeling of the Non-Quasistatic Small-Signal Response for RF-MOSFET Applications", Proceedings of the IEEE International Conference on Simulation of Semiconductor Processes and Devices (SISPAD'2002), 71-74 (2002)
* D. Navarro, K. Hisamitsu, T. Yamaoka, M. Tanaka, H. Kawano, H. Ueno, M. Miura-Mattausch, H.J. Mattausch, S. Kumashiro, T. Yamaguchi, K. Yamashita and N. Nakayama, "Circuit-Simulation Model of Gate-Drain-Capacitance Changes in Small-Size MOSFETs Due to High Channel-Field Gradients", Proceedings of the IEEE International Conference on Simulation of Semiconductor Processes and Devices (SISPAD'2002), 51-54 (2002)
* H.J. Mattausch, N. Omori, S. Fukae, T. Koide and T. Gyohten, "Fully-Parallel Pattern-Matching Engine with Dynamic Adaptability to Hamming or Manhattan Distance", 2002 Symposium on VLSI Circuits Digest of Technical Papers, 252-255 (2002)
* M. Miura-Mattausch,
H. Ueno, H.J. Mattausch, S. Kumashiro, T. Yamaguchi, K. Yamashita and N. Nakayama,
"HiSIM: Self-Consistent Surface-Potential
MOS-Model Valid Down to Sub-100nm Technologies", Proceedings of the IEEE
International Conference on Modeling and Simulation of Microsystems (MSM'2002),
678-681 (2002)
Invited Paper
* H. Kawano, M. Nishizawa, S. Matsumoto, S. Mitani, M. Tanaka, N. Nakayama, H. Ueno, M. Miura-Mattausch and H.J. Mattausch, "A Practical Small-Signal Equivalent Circuit Model for RF-MOSFETs Valid up to the Cut-Off Frequency", Proceedings of the IEEE International Microwave Symposium (IMS'2002), 2121-2124 (2002)
Publications in 2001
* N. Omori and H.J. Mattausch, "Compact central arbiters for memories with multiple ports", IEE Electronics Letters 37, 811-813 (2001)
* H.J. Mattausch, K. Kishi and T. Gyohten, "Area-efficient multi-port SRAMs for on-chip data-storage with high random-access bandwidth", IEICE Trans. on Electronics, vol. E84-C, 410-417 (2001)
* M. Miura-Mattausch, H.J. Mattausch, N. D. Arora, and C. Y. Yang, "Towards Sub-100nm MOSFET Models for Circuit Simulation", IEEE Circuits and Devices Magazine 17 (6), 29-36 (2001)
* M. Miura-Mattausch, M. Suetake, H.J. Mattausch, S. Kumashiro, N. Shigio, S. Odanaka, and N. Nakayama, "Physical Modeling of the Reverse-Short-Channel Effect for Circuit Simulation", IEEE Trans. on Electron Devices 48, 2449-2452 (2001)
* H.J. Mattausch, M. Miura-Mattausch, H. Ueno, S. Kumashiro,
T. Yamaguchi, K. Yamashita and N. Nakayama, "HiSIM:
The First Complete Drift-Diffusion MOSFET Model for Circuit Simulation",
Proceedings of the International Conference on Solid-State and
Integrated-Circuit Technology (ICSICT'2001), 861-866 (2001)
Invited Paper
* K. Morikawa, H. Ueno, D. Kitamaru, M. Tanaka, T. Okagaki, M. Miura-Mattausch, H.J. Mattausch, S, Kumashiro, T. Yamaguchi, K. Yamashita and N. Nakayama, "Enhanced Quantum Effect for Sub-100nm Pocket Technologies and its Relevance for the On-Current Condition", Extended Abstracts of the 2001 International Conference on Solid State Devices and Materials (SSDM'2001), 384-385 (2001)
* D. Kitamaru, H. Ueno, K. Morikawa, M. Tanaka, M. Miura-Mattausch, H.J. Mattausch, S. Kumashiro, T. Yamaguchi, K. Yamashita and N. Nakayama, "Vth-Model of Pocket-Implant MOSFETs for Circuit Simulation", Proceedings of the IEEE International Conference on Simulation of Semiconductor Processes and Devices (SISPAD'2001), 392-395 (2001)
* S. Matsumoto, H.J. Mattausch, S. Ooshiro, Y. Tatsumi, M. Miura-Mattausch, S. Kumashiro, T. Yamaguchi, K. Yamashita and N. Nakayama, "Test-Circuit-Based Extraction of Inter- and Intra-Chip MOSFET-Performance Variations for Analog-Design Reliability", IEEE Custom Integrated Circuits Conference Digest of Tech. Papers (CICC'2001), 357-360 (2001)
* H.J. Mattausch, T. Gyohten, Y. Soda and T. Koide, "An Architecture for Compact Associative Memories with Deca-ns Nearest-Match Capability up to Large Distances", IEEE International Solid-State Circuits Conference Digest of Tech. Papers (ISSCC'2001), 170-171 (2001)
* D. Miyawaki,
S. Matsumoto, H.J. Mattausch, S. Ooshiro, M. Suetake, M. Miura-Mattausch, S. Kumashiro, T.
Yamaguchi, K. Yamashita and N. Nakayama, "Correlation Method of
Circuit-Performance and Technology-Fluctuations for Improved Design
Reliability", Proceedings of the Asia and South Pacific Design Automation
Conference (ASP-DAC'2001), 39-44 (2001)
Best-Paper Award
Publications in 2000
* H.J. Mattausch, H. Baumgaertner, R. Allinger, M. Kerber and H. Braun, "Electrical/Thermal Properties of Nonplanar Polyoxides and the Consequent Effects for EEPROM Cell Operation", IEEE Trans. on Electron Devices 47, 1251-1257 (2000)
* T. Ono, M. Miura-Mattausch, H. Baumgaertner and H. J. Mattausch, "Super-stable neutral electron traps in nonplanar thermal oxides on monocrystalline silicon", Appl. Phys. Lett. 76, 2298-2300 (2000)
* N. Omori, K. Kishi, T. Gyohten, J. Kim and H.J. Mattausch, "Fast and Compact Central Arbiter for High Access-Bit-Rate Multi-Port Caches", Extended Abstracts of the 2000 International Conference on Solid State Devices and Materials (SSDM'2000), 360-361 (2000)
* K. Kishi, T. Gyohten, J. Kim, H.J. Mattausch, Y. Tatsumi and S. Nara, "Super-Compact Shared-Cache Memories with Low Power Consumption for Multi-Issue Single-Chip Processors", Proceedings of the 26th European Solid-State Circuits Conference (ESSCIRC'2000), Stockholm, Sweden, September 19-21, 340-343 (2000)
* M. Tanaka, N. Tokida, T. Okagaki, M. Miura-Mattausch, W. Hansch, and H.J. Mattausch, "High performance of short-channel MOSFETs due to an elevated central-channel doping", Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC'2000), 365-370 (2000)
* M. Suetake, K. Suematsu, H. Nagakura, M. Miura-Mattausch, H.J. Mattausch, S. Kumashiro, T. Yamaguchi, S. Odanaka and N. Nakayama, "HiSIM: A drift-diffusion-based advanced MOSFET model for circuit simulation with easy parameter extraction", Proceedings of the IEEE International Conference on Simulation of Semiconductor Processes and Devices (SISPAD'2000), 261-264 (2000)