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Profile |
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| Name and Affiliation |
hjm sxsys.hiroshima-u.ac.jp
Hiroshima University
Research Center for Nanodevices and Systems
Professor
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| Education and Professional Experience |
| [Eduaction] |
| 1977 |
University of Dortmund (Germany, Master of Science) |
| 1981 |
University of Stuttgart (Germany, Doctor of Science) |
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| [Professional Experience] |
| 1978 |
Max-Planck Institute for Solid-State Research (Germany, Researcher) |
| 1982 |
Siemens AG, Central Research Laboratories (Germany, Researcher, Microelectronics) |
| 1986 |
Siemens AG, Central Research Laboratories (Project Leader) |
| 1990 |
Siemens AG, Central Research Laboratories (Group Leader) |
| 1996 |
Hiroshima University, Research Center for Nanodevices and Systems, Assoc. Professor |
| 1998 |
Hiroshima University, Research Center for Nanodevices and Systems, Professor |
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| Academic Societies |
The Institute of Electrical and Electronics Engineers Inc. (IEEE), USA
The Institute of Electronics, Information and Communication Engineers (IEICE), Japan
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| Worldclass Research Results |
Memory with high access bandwidth
Minimized-area, fully-parallel multiport memory (ESSCIRC 1997)
Circuits for high-speed pattern matching
Fully-parallel mixed analog-digital associative memory (ISSCC 2001)
Matching Engine with adaptable distance measure (VLSI Symp.2002)
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| Pioneering research results |
Device models for power-circuit simulation
Power-diode/IGBT/Thyristor models (PESC 1992,93) |
| Experience in international projects |
Toshiba/Siemens project on CMOS technology, Leader of the memory synthesizer development group (1985-86)
Leader of the joint European project (4 countries, 4 companies, 2 universities) on power-circuit simulation (1993-95)
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| Industrial and National Cooperation |
Semiconductor Academic Research Center (STARC), 2001~
Renesas Technology, 2002~
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| Important Publications |
| 1. |
H.J. Mattausch, N. Omori, S. Fukae, T. Koide and T. Gyohten, "Fully-Parallel Pattern-Matching Engine with Dynamic Adaptability to Hamming or Manhattan Distance", 2002 Symposium on VLSI Circuits Digest of Technical Papers, 252-255 (2002) |
| 2. |
H.J. Mattausch, T. Gyohten, Y. Soda and T. Koide, "Compact Associative-Memory Architecture with Fully-Parallel Search Capability for the Minimum Hamming Distance", IEEE Journal of Solid-State Circuits, 37, 218-227, (2002) |
| 3. |
H. J. Mattausch, K. Kishi and T. Gyohten, "Area-efficient multi-port SRAMs for on-chip data-storage with high random-access bandwidth", IEICE Trans. on Electronics, vol. E84-C, 410-417 (2001) |
| 4. |
H..J. Mattausch, H. Baumgaertner, R. Allinger, M. Kerber and H. Braun, "Electrical/Thermal Properties of Nonplanar Polyoxides and the Consequent Effects for EEPROM Cell Operation", IEEE Trans. on Electron Devices 47, 1251-1257 (2000) |
| 5. |
R. Kraus and H.J. Mattausch, "Status and Trends of Power Semiconductor Device Models for Circuit Simulation", IEEE Trans. on Power Electronics 13, 452-465 (1998) |
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| Laboratory Page |
http://www.rcns.hiroshima-u.ac.jp/ |
| Personal Page |
http://www.rcis.hiroshima-u.ac.jp/hjm/index-e.html
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COE Program