POSTER PDF(114KB) ENTRY FORM Date & Time: (Mon.) Jan. 29, 2006 9:00-18:30 (Tue.) Jan. 20, 2006 9:00-15:45 Place: Campus Innovation Center, International Conference Room Adrress 3-3-6, Shibaura, Minato-ku,Tokyo, Japan　＞MAP Access: 1- Use JR Yamanote line or Keihin-Touhoku line, get off at Tamachi station, walk for one min. 2- Use Toei-mita line or Asakusa line, get off at Mita station, walk for 5 min. Fee: ADMISSION FREE Banquet fee: JPY 5,000 (Payment at the appointment day) Sponsor: Hiroshima University、Research Center for Nanodevices & Systems、 21st Century COE Group Office，Tokyo Liaison Office In cooperation with IEEE Hiroshima Section The Institute of Electronics, Information and Communication Engineers,Chugoku Section Information Processing Society of Japan Chugoku Branch Supported by IEEE Tokyo Section The Japan Society of Applied Physics Chugoku-Shikoku Chapter

Greeting
I would like to give a report on a hot topic of semiconductor technology of Hiroshima University based on the final results of the COE program "Nanoelectronics for Tera-Bit Information Processing" which is going to be ended in the fiscal year 2006. I will introduce the results comprehensively including the “HiSIM” as a world-standard MOS device model, and a demonstration of a real machine based on the wireless interconnection and optical interconnection technology. All the companies working in the field of semiconductor-electronics and the university researchers are welcome for participation.

Invited Speakers
・Masataka Hirose (Head of Advance Semiconductor Research Center, Advance Industrial Science and Technology (AIST))
・Prof. Dimitri Antoniadis (Department of EECS, Microsystems Technology Laboratory, Massachusetts Institute of Technology)
・Prof. Mitsumasa Koyanagi (Research Center of Graduate School of Engineering, Touhoku University)
・Professor Toshiro Hiramoto (Research Center for Industrial Science, Tokyo University)

Program

MONDAY, JANUARY 29

9:00-12:00 OPENING SESSION 9:00 Welcome Remarks 9:10 Opening Address Taizo Muta, President, Hiroshima University 9:30 [Invited] Technology Challenges for Future CMOS Masataka Hirose, Director, Advanced Semiconductor Research Center, Advanced Industrial Science and Technology 10:15-10:30 Break 10:30 Summary of the 21st Century COE Program on Nanoelectronics for Tera-Bit Information Processing Atsushi Iwata, COE Leader, Graduate School of Advanced Sciences of the Matter, Hiroshima University 11:15 [Invited] Trends and Requirements of Future FETs Based on a Simple Physical Device Model Dimitri A. Antoniadis and Ali Khakifirooz, Massachusetts Institute of Technology 12:00-13:30 Lunch Break 13:30 -17:15 SYSTEM & DEVICE SESSION 13:30 [Invited] Reconfigurable Parallel Image Processing System Using Three-Dimensional LSI Mitsumasa Koyanagi, Takeaki Sugimura, and Tetsu Tanaka, Tohoku University 14:15 Inductor based Circuit Techniques for Chip-to-Chip Interconnect and Standing Wave Clock Generation Mamoru Sasaki, Bin Yan, Daisuke Arizono, Mitsuru Shiozaki, Atsushi Mori, and Atsushi Iwata, Graduate School of Advanced Sciences of the Matter, Hiroshima University 14:45 Low-Noise and Low-Voltage Circuit Techniques for CMOS Analog Design Takeshi Yoshida, Yoshihiro Masui, Mamoru Sasaki, and Atsushi Iwata,Graduate School of Advanced Sciences of the Matter, Hiroshima University 15:15-15:30 Break 15:30 [Invited] Nanoscale Silicon Devices Using Nanostructure Physics for VLSI Applications Toshiro Hiramoto, Kousuke Miyaji, and Masaharu Kobayashi, The University of Tokyo 16:15 Characterization of Electronic Charged States of Si-based Quantum Dots for Multi-valued MOS Memories Seiichi Miyazaki, Graduate School of Advanced Sciences of the Matter, Hiroshima University 16:45 Formation Techniques for Three-Dimensional MOS Beam-Channel Transistor Hideo Sunami and Kiyoshi Okuyama, Research Center for Nanodevices and Systems, Hiroshima University 17:15-17:20 CLOSING REMARKS 17:30-18:30 POSTER SESSION 18:30-20:00 BANQUET

TUESDAY, JANUARY 30

9:00-12:15 CIRCUITS & MODELING SESSION 9:00 Functional-Memory Architectures for Information-Processing Systems Hans J?rgen Mattausch, Tetsushi Koide, M. Anwarul Abedin, and Koh Johguchi, Research Center for Nanodevices and Systems, Hiroshima University 9:30 Functional-Memory-Based Systems Enabling Recognition and Learning Tetsushi Koide, Hans Jugen Mattausch, Ali Ahmadi, Takashi Morimoto, and Kousuke Yamaoka, Research Center for Nanodevices and Systems, Hiroshima University 10:00 Physics-Based Photodiode Model Enabling Consistent Opto-Electronic Circuit Simulation Mitiko Miura-Mattausch, Kohkichi Konno, Gaku Suzuki, Tatsuya Ezaki, Osamu Matsushima, Yoshio Mizukane, Dondee Navarro, Masataka Miyake, Norio Sadachika, and Hans J?rgen Mattausch, Graduate School of Advanced Sciences of the Matter, Hiroshima University 10:30-10:45 Break 10:45 A Single-chip Gaussian Monocycle Pulse Transmitter using 0.18 μm CMOS Technology for Intra/Interchip UWB Communication Takamaro Kikkawa, Pran Kanai Saha, Nobuo Sasaki, and Kentaro Kimoto, Research Center for Nanodevices and Systems, Hiroshima University 11:15 Optical Interconnection in Silicon LSI Shin Yokoyama, Yuichiro Tanushi, and Masato Suzuki,Research Center for Nanodevices and Systems, Hiroshima University 11:45-13:15 Lunch Break 13:15 -15:20 DEVICE & PROCESS SESSION 13:15 Ultrarapid Thermal Annealing Induced by DC Arc Discharge Plasma Jet Irradiation Seiichiro Higashi, Hirotaka Kaku, Tatsuya Okada, Takuya Yorimoto, Hideki Murakami, and Seiichi Miyazaki, Graduate School of Advanced Sciences of the Matter, Hiroshima University 13:45 Evaluation of Chemical Structures and Work Function of NiSi near the Interface between NiSi and SiO2 Hideki Murakami, Hiromichi Yoshinaga, Daisuke Azuma, Akio Ohta, Yuuki Munetaka,  Seiichiro Higashi, Seiichi Miyazaki, Takayuki Aoyama, Kimihiko Hosaka, and Kentaro Shibahara, Graduate School of Advanced Sciences of the Matter, Hiroshima University 14:15-14:30 Break 14:30 Development of Reliable High-k Gate Dielectrics for Scaled MOSFETs Anri Nakajima, Research Center for Nanodevices and Systems, Hiroshima University 15:00 Metal Gate and Junction Technologies for Leading Edge Devices Kentaro Shibahara, Research Center for Nanodevices and Systems, Hiroshima University 15:30-15:45 CLOSING REMARKS 13:15 -15:20 POSTER EXHIBITORS P-01 An Object Detection/Recognition System using a 3-Dimensional Integration with Local and Global Wireless Interconnections Hiroshi Ando, Seiji Kameda, Nobuo Sasaki, Daisuke Arizono, Kentaro Kimoto, Norimitsu Fuchigami, Kouta Kaya, Mamoru Sasaki, Takamaro Kikkawa, and Atsushi Iwata P-02 A Vision System using a 3-Dimensional Integration with Local and Global Wireless Interconnections Seiji Kameda, Nobuo Sasaki, Daisuke Arizono, Kentaro Kimoto, Masaki Odahara, Mamoru Sasaki, Takamaro Kikkawa, and Atsushi Iwata P-03 Learning Algorithms for Robots Behaving Flexibly in Dynamic Environments Masahiro Ono, Hiroshi Ando, Mamoru Sasaki, and Atsushi Iwata P-04 Window-based Stereo Matching Algorithm Using a Weighted Average of Costs Aggregated with Window Size Reduction Kan'ya Sasaki, Seiji Kameda, Hiroshi Ando, Mamoru Sasaki, and Atsushi Iwata P-05 A 0.6 V Supply CMOS Amplifier Using Noise Reduction Techniques of Autozeroing and Chopper Stabilization Yoshihiro Masui, Takeshi Yoshida, Mamoru Sasaki, and Atsushi Iwata P-06 Evaluation of Digital Crosstalk Noise to Fully Differential VCO Akihiro Toya, Yoshitaka Murasaka, Takafumi Ohmoto, and Atsushi Iwata P-07 HiSIM-SOI: Complete Surface-Potential-Based Fully-Depleted SOI-MOSFET Model for Circuit Simulation Norio Sadachika, Daisuke Kitamaru, Yasuhito Uetsuji, Dondee Navarro, Marmee Mohd Yusoff, Tatsuya Ezaki,  Hans J?rgen Mattausch, Shunsuke Baba, and Mitiko Miura-Mattausch P-08 Photoemission Study of HfO2/Ge(100) Stacked Structures Hiroshi Nakagawa, Akio Ohta, Hideki Murakami, Seiichiro Higashi, and Seiichi Miyazaki P-09 Photoemission Study of Ultrathin N incorporated Hf-Silicates on Si(100) Systems Akio Ohta, Hiroshi Nakagawa, Hideki Murakami, Seiichirou Higashi, Seiichi Miyazaki, Seiji Inumiya, and Yasuo Nara P-10 Developement of Fabrication Processes for New SOI MOS Transistor and a Silicidation Technique for Source and Drain of Vertical Channel Devices Kiyoshi Okuyama, Koji Yoshikawa, Shunpei Matsumura, Atsushi Sugimura, and Hideo Sunami P-11 A Human-memory Based Learning Model and Hardware Prototyping in FPGA Ali Ahmadi, M. Anwarul Abedin, Hans J?rgen Mattausch, Tetsushi Koide, Yoshinori Shirakawa, and M. Arifin Ritonga P-12 Application of Fully Parallel Associative Memory in Two-stage Pattern Matching M. Anwarul Abedin, Ali Ahmadi, Yuuki Tanaka, Shogo Sakakibara, Tetsushi Koide, and Hans J?rgen Mattausch P-13 Highly-Parallel Table-Lookup-Coding with Scalable Architecture using Flexible Multi-Ported Content Addressable Memory Takeshi Kumaki, Yutaka Kono, Masakatsu Ishizaki, Tetsushi Koide, and Hans J?rgen Mattausch P-14 Multi-Bank Register File for Increased Performance of Highly-Parallel Processors Koh Johguchi, Ken-ichi Aoyama, Tetsuya Sueyoshi, Moto Maeda, Hans J?rgen Mattausch, Tetsushi Koide, Tetsuo Hironaka, and Kazuya Tanigawa P-15 FPGA Implementation of Object-Based Real-Time Object Tracking Architecture Kousuke Yamaoka, Takashi Morimoto, Hidekazu Adachi, Kazutoshi Awane, Tetsushi Koide, and Hans J?rgen Mattausch P-16 A Single-chip Ultra-Wideband Receiver using Silicon Integrated Antennas for Inter-chip Wireless Interconnection Nobuo Sasaki, Masashi Fukuda, Masakazu Nitta, Kentaro Kimoto, and Takamaro Kikkawa P-17 On-Chip Wireless Signal Transmission using Si Integrated Antennas Kentaro Kimoto, Masakazu Nitta, Nobuo Sasaki, and Takamaro Kikkawa P-18 Workfunction Tuning of NiSi and Pd2Si Fully-Silicided Gates by Predoping Takuji Hosoi, Kosuke Sano, Masaki Hino, and Kentaro Shibahara P-19 Ring Resonator Optical Switches for Interconnection on Si Chips Yuichiro Tanushi and Shin Yokoyama P-20 Monolithic Mach-Zehnder Optical Modulator Using Electro-Optic Material: (Ba,Sr)TiO3 Film Sputter Deposited at Low Temperature on Silicon Masato Suzuki, Yuichiro Tanushi, Kazuma Nagata, and Shin Yokoyama P-21 Atomic-Layer-Deposition of HfO2 on Si and Ge Substrates from Hafnium Tetrakis(ethylmethylamino) and Water Shiyang Zhu and Anri Nakajima