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3rd COE Workshop Proceeding 2004/12/6

PDF[110MB]

Cover & Back cover PDF[2.2MB]
Inside cover PDF[50KB]
Preface PDF[72KB]
Contents

PDF[109KB]

PLENARY SESSION

Recent Progress of the COE
Atsushi Iwata, COE Leader, Graduate School of Advanced Sciences of Matter, Hiroshima University

PDF[3.8MB]

[Invited] Characterization and optimization of Cu-Low k for 45nm and beyond
Karen Maex, IMEC, Katholik University, Leuven, Belgium

PDF[8.1MB]
[Invited] Design with On-Chip Interconnect Inductance
S. Simon Wong, Stanford University, CA, USA
PDF[1.5MB]

[Invited] Recent Advances of Diagnoses and Therapeutics in Practical Medicine
Nobuoki Kohno, Graduate School of Biomedical Sciences, Hiroshima University

PDF[5MB]

[Invited] Advanced RF/Baseband Interconnects for Future ULSI Communications
Mau-Chung Frank Chang, University of California, Los Angeles, CA, USA

PDF[1MKB]

[Invited] Wireless Communications Using Integrated Antennas
Kenneth K. O, University of Florida, FL, USA

PDF[2.7MB]

ULSI Wireless Interconnection using Integrated Antennas for UWB Signal Transmission
Takamaro Kikkawa, Research Center for Nanodevices and Systems, Hiroshima University

PDF[948KB]
POSTER SESSION

P-01 Three Dimensional Integration Architecture for Tera-bit Information processing
A. Iwata, M. Sasaki, T. Yoshida, S. Kameda, H. Ando, M. Shiozaki, M. Ono and K. Sasaki

PDF[575KB]

P-02  A Wireless Chip Interconnect Using Resonant Coupling Between Spiral Inductors
Mamoru Sasaki, Daisuke Arizono and Atsushi Iwata

PDF[306KB]

P-03  A Low-Noise Circuit Technique for Sensing the Nerve Signals
T. Yoshida, T. Mashimo, A. Iwata, M. Yoshida and K. Uematsu

PDF[1.4MB]

P-04  A Brain-type Multi-chip Vision System with a PWM-based Line Parallel Interconnection
Seiji Kameda, Masaki Odahara and Atsushi Iwata

PDF[4MB]

P-05  A Prototype Software System for Multi-object Recognition and its FPGA Implementation
H. Ando, N. Fuchigami, M. Sasaki and A. Iwata

PDF[8.8MB]

P-06  A 2.7Gcps and 7-multiplexing CDMA Serial Communication Chip for Real-time Robot Control
Mitsuru Shiozaki, Toru Mukai, Masahiro Ono, Mamoru Sasaki and Atsushi Iwata

PDF[13.1KB]

P-07  A Module based Robust Learning System to Environmental Change for Robot Brain
Masahiro Ono, Mamoru Sasaki and Atsushi Iwata

PDF[2.1KB]

P-08  A Stereoscopic System with Integration of Multiple Features
Kan'ya Sasaki, Seiji Kameda, Hiroshi Ando, Mamoru Sasaki and Atsushi Iwata

PDF[313KB]

P-09 Associative Memory-Based Systems with Recognition and Learning Capability
H. J. Mattausch, T. Koide

PDF[3.8MB]

P-10 Real-Time Character Recognition System Using Associative Memory Based Hardware
A. Ahmadi, Y. Shirakawa, M. A. Abedin, K. Takemura, K. Kamimura, H. J. Mattausch, and T. Koide

PDF[1.6MB]

P-11 Low-Power Video Segmentation by Pipeline Processing of Tiled Images
T. Morimoto, H. Adachi, O. Kiriyama, Z. Zhu, T. Koide, and H. J. Mattausch

PDF[847KB]

P-12 Efficient Object Tracking Algorithm using Image Segmentation and Pattern Matching
O. Kiriyama, T. Morimoto, H. Adachi, Z. Zhu, T. Koide, and H. J. Mattausch

PDF[1.1MB]

P-13 Multi-view Face Detection and Recognition using Haar-like Features
Z. Zhu, T. Morimoto, H. Adachi, O. Kiriyama, T. Koide, and H. J. Mattausch

PDF[363KB]

P-14 Unified Data/Instruction Cache with Bank-Based Multi-Port Architecture
K. Johguchi, Z. Zhu, H. J. Mattausch, T. Koide, and T. Hironaka

PDF[566KB]

P-15 Multi-bank based Switch Architecture with Flexible Scheduled Buffering of Packets
T. Fujii, K. Kobayashi, T. Koide, H. J. Mattausch, and T. Hironaka

PDF[308KB]

P-16 A Carrier Transit Time Delay-Based Non-Quasi-Static MOSFET Model for Circuit-Simulation
Dondee Navarro, N. Nakayama, Y. Takeda, M. Miura-Mattausch, H. J. Mattausch, T. Ohguro,T. Iizuka,M. Taguchi and S. Miyamoto

PDF[432KB]

P-17 Frequency-Domain-Based Carrier Transport Model for a Lateral p-i-n photodiode
Kohkichi Konno, Osamu Matsushima, Kiyohito Hara, Gaku Suzuki, Dondee Navarro and Mitiko Miura-Mattausch

PDF[1.5MB]

P-18 Fully-Depleted SOI-MOSFET Model for Circuit Simulation and its Application to 1/f Noise Analysis
N. Sadachika, Y. Uetsuji, D. Kitamaru, L. Weiss, U. Feldmann, S. Baba, H. J. Mattausch and M. Miura-Mattausch

PDF[806KB]

P-19  A TH-UWB Transmitter and its Pulse Generation Circuit for Intra/Interchip Wireless Interconnection
Pran Kanai Saha, Nobuo Sasaki and Takamaro Kikkawa

PDF[1.1MB]

P-20  Design and Measurement of On-Chip CMOS UWB Receiver
Nobuo Sasaki, Pran Kanai Saha and Takamaro Kikkawa

PDF[1.7MB]

P-21  Transmission characteristics of Gaussian monocycle pulse for inter-chip wireless interconnection using integrated antenna
K. Kimoto and T. Kikkawa

PDF[1MB]

P-22  RF Measurement of Permittivity of Low-k films on Si
K. Isari and T. Kikkawa

PDF[465KB]

P-23  Photosensitive porous low-k interlayer dielectric film
Shin-Ichiro Kuroki and Takamaro Kikkawa

PDF[671KB]

P-24  Effect of Hexamethyldisilazane on Moisture Adsorption of Porous Silica Films
Shin-Ichiro Kuroki and Takamaro Kikkawa

PDF[2.9MB]

P-25 Single-Metal Tunable-Workfunction Technology with NiSi and Mo Gate Electrode
T. Hosoi, K. Sano, M. Hino, N. Ooishi and K. Shibahara

PDF[1.5MB]

P-26 Green laser annealing with metal absorber
K. Shibahara, A. Matsuno, E. Takii, K. Kurobe and T. Eto

PDF[704KB]

P-27 Low-Resistive and Low Leak Current Ultra-Shallow n+/p Junction Formed by Heat-Assisted Excimer Laser Annealing
Ken-ichi Kurobe, Yoshinori Ishikawa, Takanori Eto, Akira Matsuno, and Kentaro Shibahara

PDF[1.4MB]

P-28 Study in 3-D MOS Transistor Formation
Kiyoshi Okuyama, Kei Kobayashi, Shunpei Matsumura, Koji Yoshikawa and Hideo Sunami

PDF[932KB]

P-29  Novel Doping Profile Evaluation for 3-D MOS Transistor
Kei Kobayashi, Takanori Eto, Kiyoshi Okuyama, Kentaro Shibahara, and Hideo Sunami

PDF[870KB]

P-30 Characterization of 1.55-μm Infrared Light Propagation in SOI Waveguide
Masato Kawai, Tetsuo Tabei, and Hideo Sunami

PDF[1.7MB]

P-31 Characterization of Charged States of Silicon-Based Quantum Dots and Its Application to Floating Gate MOS Memories
S. MIYAZAKI

PDF[2.3MB]

P-32  Characterization of Atom Diffusion in Polycrystalline Si/SiGe/Si Stacked Gate
H. Murakami, Y. Moriwaki, M. Fujitake, D. Azuma, S. Higashi and S. Miyazaki

PDF[4.1MB]

P-33  Crystallization of Amorphous Si films on Glass Substrate Using Plasma Jet and Its Application to Thin Film Transistor Fabrication
S. Higashi, H. Kaku, T. Okada, H. Taniguchi, H. Murakami and S. Miyazaki

PDF[946KB]

P-34  Local Electronic Transport through Si Dot with Ge Core as Detected by AFM Conductive Probe
Yudi Darma and Seiichi Miyazaki

PDF[2.5MB]

P-35  Fabrication of Multiply-Stacked Structures of Si Quantum-Dots Embedded in SiO2 by Combination of Low-Pressure CVD with Remote Plasma Treatments
K. Makihara, H. Nakagawa, M. Ikeda, H. Murakami, S. Higashi and S. Miyazaki

PDF[7.1MB]

P-36  High-Rate Growth of Highly-Crystallized Si Films from VHF Inductively-Coupled Plasma CVD
Nihan Kosku and Seiichi Miyazaki

PDF[614KB]

P-37 Electrical characterization of HfAlOx/SiON dielectric gate capacitors
Yanli Pei, S. Nagamachi, H. Murakami, S. Higashi, S. Miyazaki, T. Kawahara and K.Torii

PDF[1.2MB]

P-38  Characterization of Interfacial Oxide Layers in Heterostructures of Hafnium Oxides Formed on NH3-nitrided Si(100)
H. Nakagawa, A. Ohta, F. Takeno, S. Nagamachi, H. Murakami, S. Higashi and S. Miyazaki

PDF[1.2MB]

P-39  Charging and Discharging Characteristics of Stacked Floating Gates of Silicon Quantum Dots
T. Shibaguchi, M. Ikeda, H. Murakami and S. Miyazaki

PDF[1.1MB]

P-40  Photo-Induced Electron Charging to Silicon-Quantum-Dot Floating Gate in Metal-Oxide-Semiconductor Memories
T. Nagai, M. Ikeda, H. Murakami, S. Higashi and S. Miyazaki

PDF[1.4MB]

P-41  Technology for Optical Interconnection in LSI
Shin Yokoyama, Yuichiro Tanushi, Zhimou Xu, Masato Suzuki, and Keita Wakushima

PDF[897KB]

P-42  Simulation of Ring Resonator Optical Switches
Yuichiro Tanushi and Shin Yokoyama

PDF[600KB]

P-43  Effect of annealing on the structural properties of spin-coated Ba0.7Sr0.3TiO3 films
Zhimou Xu, Yuichiro Tanushi, Masato Suzuki, Keita Wakushima and Shin Yokoyama

PDF[675KB]

P-44  Effect of H2 adding and substrate bias to Cu sputtering
Masahiro Ooka and Shin Yokoyama

PDF[848KB]

P-45  Anomalous Behavior of Interface Traps of Si MOS Capacitors Contaminated with Organic Molecules
Masato Suzuki and Shin Yokoyama

PDF[450KB]

P-46  Development of nano-size mask for diamond emitter
Tetsuo Tabei, Tomihito Miyazaki, Yoshiki Nishibayashi and Shin Yokoyama

PDF[2.1MB]

P-47 Interface Trap Generation on MOSFETs with Thin SiO2 and Plasma-Nitrided SiO2 Gate Dielectrics under Static and Dynamic Stresses
Shiyang Zhu, Anri Nakajima, Takuo Ohashi and Hideharu Miyake

PDF[366KB]

P-48 Room Temperature Operation of an Exclusive-OR Circuit Using a Highly-Doped Si Single-Electron Transistor
Tetsuya Kitade, Kensaku Ohkura and Anri Nakajima

PDF[1MB]

P-49 Atomic-layer deposition of ultrathin gate dielectrics and Si new functional devices
Anri Nakajima

PDF[651KB]

P-50 [Invited] Non-Contact Impedance Sensor
Makoto Kaneko, Tomohiro Kawahara and Yukio Hosaka

PDF[4.3MB]