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2000 (2000 April - 2001 March)

  1. Advanced device process and material technologies for ULSI
  2. Self assembling technique and quantum structure
  3. Light emitting devices
  4. Technologies for intelligent systems

1 Advanced device process and material technologies for ULSI

 

 

1.1 Fabrication and evaluation techniques for scaled MOS devices

[00-1] K. Shibahara, K. Egusa, K. Kamesaki, and H. Furumoto, "Improvement in Antimony-Doped Ultra Shallow Junction Sheet Resistance by Dopant Pileup Reduction at the SiO2 /Si Interface," Jpn. J. Appl. Phys. Vol. 39 (2000), pp. 2194-2197.

[00-2] K. Shibahara and D. Onimatsu, "Antimony Clustering due to High Dose Implantation," Mat. Res. Soc. Symp. Proc. Vol. 610, pp. B8.5.1-B8.5.6.

[00-3] S. Nakamura, M. Itano, H. Aoyama, K. Shibahara, S. Yokoyama, and M. Hirose, "Comparative Studies of PFC alternative Gas Plasmas for Contact Hole Etch," Proc. of 22th Symp. on Dry Process (2000) pp. 199-204.

[00-4] M. Koh, W. Mizubayashi, K. Iwamoto, H. Murakami, T. Ono, M. Tsuno, T. Mihara, K. Shibahara, S. Miyazaki, and M. Hirose, "Limit of Gate Oxide Thickness Scaling in MOSFETs due to Apparent Threshold Voltage Fluctuation Induced by Tunnel Leakage Current," IEEE Trans. Electron Devices, Vol.48 (2001), pp. 259-264.

[00-5] T. Hatano, Y. Ito, A. Nakajima, and S. Yokoyama, "Fabrication of Novel Double-Barrier MOS Transistors with Poly-Si Dots," Proc. of 2000 Int. Symp. on Formation, Phys. and device Application of Quantum Dot Structures (2000), p. 10.

[00-6] T. Hatano, Y. Itoh, A. Nakajima, and S. Yokoyama, "Fabrication Technologies for Double-SiO2-Barrier MOS Transistor with a Poly-Si Dot," Jpn. J. Appl. Phys. Vol. 40 (2001), pp. 2017-2020.

[00-7] H.J. Mattausch, H. Baumgärtner, R. Allinger, M. Kerber, and H. Braun, "Electrical/Thermal Properties of Nonplanar Polyoxides and the Consequent Effects for EEPROM Cell Operation," IEEE Trans. on Electron Devices Vol. 47 (2000), pp. 1251-1257.

[00-8] T. Ono, M. Miura-Mattausch, H. Baumgärtner, and H. J. Mattausch, "Super-stable neutral electron traps in nonplanar thermal oxides on monocrystalline silicon," Appl. Phys. Lett. Vol. 76 (2000), pp. 2298-2300.

[00-9] M. Suetake, K. Suematsu, H. Nagakura, M. Miura-Mattausch, H.J. Mattausch, S. Kumashiro, T. Yamaguchi, S. Odanaka, and N. Nakayama, "HiSIM: A drift-diffusion-based advanced MOSFET model for circuit simulation with easy parameter extraction," Proc. of the Int. Conf. on Simulation of Semiconductor Processes and Devices (SISPAD2000) (2000), pp. 261-264.

[00-10] D. Miyawaki, S. Matsumoto, H.J. Mattausch, S. Ooshiro, M. Suetake, M. Miura-Mattausch, S. Kumashiro, T. Yamaguchi, K. Yamashita, and N. Nakayama, "Correlation Method of Circuit-Performance and Technology-Fluctuations for Improved Design Reliability," Best-Paper Award, Proc. of the Asia and South Pacific Design Automation Conf. (ASP-DAC2001) (2001), pp. 39-44.

 

1.2 Gate oxide and reliability issues

[00-11] M. Hirose, M. Koh, W. Mizubayashi, H. Murakami, K.Shibahara, and S. Miyazaki "Fundamental Limit of Gate Oxide Thickness Scaling in Advanced MOSFETs," Semiconductor Science and Technology, 15 (2000) pp. 485-490.

[00-12] M. Hirose, W. Mizubayashi, Khairurrijal, M. Ikeda, H. Murakami, A. Kohno, K. Shibahara, and S. Miyazaki, "Ultrathin Gate Dielectrics for Silicon Nanodevices," Superlattices and Microstructures, Vol. 27 (2000) pp. 383-393.

[00-13] Khairurrijal, W. Mizubayashi, S. Miyazaki, and M. Hirose, "Analytic Model of Direct Tunnel Current through Ultrathin Gate Oxide," J. Appl. Phys., Vol. 87 (2000) pp. 3000-3005.

[00-14] S. Miyazaki, T. Tamura, M. Ogasawara, H. Itokawa, H. Murakami, and M. Hirose, "Influence of Nitrogen Incorporation in Ultrathin SiO2 on the Structure and Electronic States of the SiO2/Si(100) Interface," Appl. Surf. Sci. Vol. 159 (2000) pp. 75-82.

[00-15] H. Murakami, T. Mihara, S. Miyazaki, and M. Hirose, "Etch Damage of n+Poly-Si Gate Side Wall as Evaluated by Gate Tunnel Leakage Current," Extend. Abst. of the 2000 Int. Conf. on Solid State Devices and Materials(SSDM2000), (2000) pp. 194-195.

[00-16] W. Mizubayashi, Y. Yoshida, M. Narasaki, S. Miyazaki, and M. Hirose, "Temperature-Dependent Soft Breakdown in Ultrathin Gate Oxides," Extend. Abst. of the 2000 Int. Conf. on Solid State Devices and Materials(SSDM2000), (2000) pp. 244-245.

[00-17] Khairurrijal, W. Mizubayashi, S. Miyazaki, and M. Hirose, "Unified Analytic Model of Direct and Fowler-Nordheim Tunnel Currents Through Ultrathin Gate Oxides," Appl. Phys. Lett., Vol. 77 (2000) pp. 3580-3582.

[00-18] W. Mizubayashi, H. Itokawa, S. Miyazaki, and M. Hirose, "Soft Breakdown Mechanism in Ultrathin Gate Oxides," The Phys. and Chemistry of SiO2 and the Si-SiO2 Interface-4, (2000) pp. 409-417.

[00-19] W. Mizubayashi, Y. Yoshida, S. Miyazaki, and M.Hirose, "Soft Breakdown of Ultrathin Gate Oxides," Abst. of Joint Workshop of 29th IUVSTA Int. Workshop on Selective and Functional Film Deposition Technologies as Applied to ULSI Technology and 2nd Int. Workshop on Development of Thin Films for Future ULSI's and Nano-Scale Process Integration, (2000) pp. 204-206.

[00-20] H. Murakami, T. Mihara, S. Miyazaki, and M.Hirose, "Depletion at n+poly-Si Gate Side Wall/SiO2 Interfaces as Evaluated by Gate Tunnel Leakage Current," Abst. of Joint Workshop of 29th IUVSTA Int. Workshop on Selective and Functional Film Deposition Technologies as Applied to ULSI Technology and 2nd Int. Workshop on Development of Thin Films for Future ULSI's and Nano-Scale Process Integration, (2000) pp. 201-203.

[00-21] M. Hirose, Khairurrijal, M. Ikeda, H. Murakami, A. Kohno, K Shibahara, and S. Miyazaki, "Tunneling in Ultrathin Gate Oxides and Related Properties of Silicon Nanodevices," Abst. of Silicon Nanoelectronics Workshop, (2000) pp. 6-6A.

 

1.3 Interconnect Technologies

[00-22] T. Kikkawa, "Current and Future Development of Low-k Dielectrics for Cu Interconnects," Technical Digest of Int. Electron Devices Meeting (IEDM), IEEE, New York, 2000, pp. 253-256.

[00-23] T. Kikkawa, T. Nagahara, and H. Matsuo, "Direct Patterning of Photosensitive Low-Dielectric-Constant Films Using Electron-Beam Lithography," Appl. Phys. Lett.s, Vol. 78 (2001) pp. 2557-2559.

[00-24] S. Mukaigawa, T. Aoki, Y. Shimizu, and T. Kikkawa, "Measurement of Copper Drift in Methylsilsesquiazane-Methylsilsesquioxane Dielectric Films," Jpn. J. Appl. Phys. Vol. 39 (2000), pp. 2189-2193.

[00-25] 吉川公麿, "多層配線技術とスケーリング," 電子情報通信学会論文誌C, Vol. J83-C (2000), pp. 105-117.

[00-26] K.S.R. Koteswara Rao, T. Katayama, S. Yokoyama, and M. Hirose, "Optimum Atomic Spacing for AlAs Etching in GaAs Epitaxial Lift-Off Technology," Jpn. J. Appl. Phys. Vol. 39 (2000), pp. L457-L459.

 

1.4 CVD and Si epitaxial technologies

[00-27] M. Adachi, T. Fujimoto, Y. Itoh, and K. Okuyama, "Numerical Simulations of Films Formed by Cluster/Particle Co-Deposition in Atmospheric-Pressure Chemical Vapor Deposition Process Using Organic Silicon Vapors and Ozone Gas," Jpn. J. Appl. Phys., Vol. 39 (6A) (2000), pp. 3542-354.

[00-28] T. Fujimoto,Y. Itoh, K. Okuyama, S. Yamada, T. Murakami, and F. G. Shi, "Chemical Reaction Kinetics and Growth Rate of (Ba, Sr) TiO3Films Prepared by Liquid Source Chemical Vapor Deposition Method," J. Electrochem. Soc., Vol. 147 (7) (2000), pp. 2581-2588.

[00-29] T. Fujimoto, K. Okuyama, M. Shimada, and Y. Fujishige, "Particle Generation and Thin Film Surface Morphology in Tetraethylorthosilicate/Oxygen Plasma Enhanced Chemical Vapor Deposition Process," J. Appl. Phys., Vol. 88 (5) (2000), pp. 3047-3052.

 

1.5 Atomic scale process

[00-30] S. Yokoyama, K. Ohba, K. Kawamura, T. Kidera and A. Nakajima, "Low-Temperature Selective Deposition of Silicon by Time-Modulation Exposure of Disilane and Formation of Silicon Nanowires," Extend. Abst. of the Int. Conf. on Solid State Devices and Materials (SSDM2000), (2000) pp. 202-203.

[00-31] A. Nakajima, T. Yoshimoto, T. Kidera, K. Obata, S. Yokoyama, H. Sunami, and M. Hirose, "Atomic-Layer-Deposited Silicon Nitride/SiO2 Stacked Gate Dielectrics for Highly Reliable p-MOSFETs," Appl. Phys. Lett. Vol. 77 (2000), pp. 2855-2857.

 

1.6 High-k dielectrics

[00-32] S. Miyazaki, H. Itokawa, M. Ogasawara, M. Narasaki, H. Yamashita, and M. Hirose, "Characterization of Ultrathin Gate Dielectrics Using Photoelectron Spectroscopy," Abst. of Joint Workshop of 29th IUVSTA Int. Workshop on Selective and Functional Film Deposition Technologies as Applied to ULST Technology and 2nd Int. Workshop on Development of Thin Films for Future ULSI's and Nano-Scale Process Integration, (2000) pp. 67-70.

 

1.7 Contamination control

[00-33] T. Yoshino, S. Yokoyama, T. Suzuki and T. Fujii, "Influence of Organic Contaminant on Breakdown Characteristics of MOS Capacitors with Thin SiO2," Extend. Abst. of the Int. Conf. on Solid State Devices and Materials (SSDM2000), (2000) pp. 552-553.

[00-34] 吉野雄信、横山　新、藤井敏昭、鈴木　作、"半導体搬送ボックスのUV/光電子法によるクリーン化とMOSデバイスへの影響," エアロゾル研究, 第16巻, 第1号 (2001) pp. 57-64.

[00-35] Habuka, H., M. Shimada, and K. Okuyama, "Rate Theory of Multicomponent Adsorption of Organic Species on Silicon Wafer Surface," J. Electrochem. Soc., Vol. 147 (6) (2000), pp. 2319-2323.

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2 Self assembling technique and quantum structure

 

 

2.1 Si quantum dot

[00-36] S. Miyazaki, Y. Hamamoto, E. Yoshida, M. Ikeda, and M. Hirose, "Control of Self-Assembling Formation of Nanometer Silicon Dotrs by Low Pressure Chemical Vapor Deposition," Thin Solid Films, Vol. 369 (2000), pp. 55-59.

[00-37] N. Shimizu, M. Ikeda, E. Yoshida, S. Miyazaki, and M. Hirose, "Charging States of Si Quantum Dots as Detected by AFM/Kelvin Probe Technique," Jpn. J. Appl. Phys., Vol. 39 (2000), pp. 2318-2320.

[00-38] Y. Hirano, F. Sato, N. Saito, M. Abe, S. Miyazaki, and M. Hirose, "Fabrication of Nanometer Sized Si dot Multilayers and Their Photoluminescence Properties," Journal of Non-Crystal Solids, Vol. 266-269 (2000), pp. 1004-1008.

[00-39] A. Kohno, H. Murakami, H. Nishiyama, S. Miyazaki, and M. Hirose, "Transient Characteristics of Electron Charging in Si-Quantum-Dot Floating Gate MOS Memories," Extend. Abst. of the 2000 Int. Conf. on Solid State Devices and Materials(SSDM2000), (2000), pp. 124-125.

 

2.2 Al nanoscale structure

[00-40] S.Shingubara, T.Osaka, H.Sakaue, T.Takahagi, and A.H.Verbruggen,"Electromigration Induced Edge Drift Velocity Measurement by Blech Pattern Attached with Multiple Voltage Probes," Advanced Metallization Conf. 1999, Mat. Res. Soc. Proc. (2000), pp. 727－733

[00-41] Y.Murakami, S.Shingubara, H.Sakaue, and T.Takahagi, "Al Dot Hexagonal Array Formation using Anodic Oxidation and Bselective Etching," Proc. of Microprocesses and Nanotechnology 2000, (2000), pp. 178-179.

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3 Light emitting devices

[00-42] H. Sumitomo, M. Yamanishi, and Y. Kadoya, "Photon-Number Squeezing in a Light-Emitting Diode Driven by a Constant-Voltage Source: Pump Regulation by the Non-Coulombic Effect," Jpn. J. Appl. Phys. Pt.2, Vol. 39 (11B) (2000), pp. L1167-L1170.

[00-43] M. Kobayashi, Y. Kadoya, H. Yuji, R. Masuyama, and M. Yamanishi, "Squeezing of photon-number fluctuations in the frequency range wider than 300MHz in light-emitting diodes at room temperature," J. Opt. Soc. Am. B Vol. 17 (7) (2000), pp. 1257-1262.

[00-44] H. Sumitomo, M. Yamanishi, and Y. Kadoya, "Generation of Heralded Twin-Photons in a Series-Coupled Mesoscopic Light-Emitting Diode System," Jpn. J. Appl. Phys. Pt.2, Vol. 40 (2A) (2001), pp. L85-L88.

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4 Technologies for intelligent systems

[00-45] N. Omori, K. Kishi, T. Gyohten, J. Kim, and H.J. Mattausch, "Fast and Compact Central Arbiter for High Access-Bit-Rate Multi-Port Caches," Extend. Abst. of the 2000 Int. Conf. on Solid State Devices and Materials (SSDM2000), (2000) pp. 360-361.

[00-46] K. Kishi, T. Gyohten, J. Kim, H.J. Mattausch, Y. Tatsumi, and S. Nara, "Super-Compact Shared-Cache Memories with Low Power Consumption for Multi-Issue Single-Chip Processors," Proc. of the 26th European Solid-State Circuits Conf. (ESSCIRC2000), (2000) pp. 340-343.

[00-47] H.J. Mattausch, K. Kishi, and T. Gyohten, "Area-efficient multi-port SRAMs for on-chip data-storage with high random-access bandwidth," IEICE Trans. on Electronics, Vol. E84-C (2001), pp. 410-417.

[00-48] H.J. Mattausch, T. Gyohten, Y. Soda, and T. Koide, "An Architecture for Compact Associative Memories with Deca-ns Nearest-Match Capability up to Large Distances," IEEE Int. Solid-State Circuits Conf. Digest of Tech. Papers (ISSCC2001), (2001), pp. 170-171.

[00-49] T. Morie, T. Matsuura, S. Miyata, T. Yamanaka, M. Nagata,, and A. Iwata, "Quantum Dot Structures Measuring Hamming Distance for Associative Memories," Superlattices and Microstructures, Vol. 27 (2000), pp. 613-616.

[00-50] T. Yamanaka, T. Morie, M. Nagata, and A. Iwata, "A Single-Electron Stochastic Associative Processing Circuit Robust to Random Background-Charge Effects and its Structure Using Nanocrystal Floating-Gate Transistors," Nanotechnology, Vol. 11 (2000), pp. 154-160.

[00-51] M. Nagata, J. Nagai, T. Morie, and A. Iwata, "Measurements and Analyses of Substrate Noise Waveform in Mixed Signal IC Environment," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 19 (2000), pp. 671-678.

[00-52] T. Morie, S. Sakabayashi, M. Nagata, and A. Iwata, "CMOS Circuits Generating Arbitrary Chaos by Using Pulse Width Modulation Techniques," IEEE Trans. on Circuits and Systems-I, Vol. 47 (2000), pp. 1652-1657.

[00-53] M. Nagata, J. Nagai, T. Morie, and A. Iwata, "Quantitative Characterization of Substrate Noise for Physical Design Guides in Digital Circuits," Proc. of IEEE 2000 Custom Integrated Circuits Conf., pp. 95-98.

[00-54] A. Iwata, M. Nagata, N. Takeda, M. Homma, and T. Morie, "Pulse Modulation Circuit Architecture and its Application to Functional Image Sensors," Proc. IEEE Int. Symp. on Circuits and Systems 2000, pp. II-301-304.

[00-55] T. Matsuura, T. Morie, M. Nagata, and A. Iwata, "A Multi-Quantum-Dot Associative Circuit Using Thermal-Noise Assisted Tunneling," Extend. Abst. of the 2000 Int. Conf. Solid State Devices and Materials (SSDM2000), (2000) pp. 306-307.

[00-56] K. Katayama, M. Nagata, T. Morie, and A. Iwata, "A High-Resolution Hadamard Transform Circuit Using Pulse Width Modulation Technique," Extend. Abst. of the 2000 Int. Conf. Solid State Devices and Materials (SSDM2000), (2000) pp. 366-367.

[00-57] H. Ando, T. Morie, M. Miyake, M. Nagata, and A. Iwata, "Image Object Extraction using Resistive-Fuse and Oscillator Networks and a Pulse-Modulation Circuit for their LSI Implementation," Extend. Abst. of the 2000 Int. Conf. Solid State Devices and Materials (SSDM2000), (2000) pp. 368-369.

[00-58] T. Morie, M. Miyake, S. Nishijima, M. Nagata, and A. Iwata, "A Multi-Functional Cellular Neural Network Circuit Using Pulse Modulation Signals for Image Recognition," Proc. 7th Int. Conf. on Neural Information Processing (ICONIP-2000), pp. 613-617.

[00-59] T. Morie, T. Matsuura, M. Nagata, and A. Iwata, "Quantum Dot Structures Measuring Hamming Distance for Associative Memories," Extend. Abst., 4th Int. Workshop on Quantum Functional Devices (QFD2000), pp. 210-213.

[00-60] 岩田穆, 永田真, "アナログディジタル回路混在チップの低雑音設計技術," 電子材料，Vol. 39 (2000), pp. 23-28.

[00-61] 永田真, 岩田穆, "基板ノイズを低減するデジタル回路の新設計法," エレクトロニクス，Vol. 45 (2000), pp. 1-4.

[00-62] A. Iwata, T. Morie, and M. Nagata "Merged Analog-Digital Circuits Using Pulse Modulation for Intelligent SoC Applications," IEICE Trans. on Fundamentals, Vol. E84-A (2001), pp. 486-496.

[00-63] M. Nagata, J. Nagai, K. Hijikata, T. Morie, and A. Iwata, "Physical Design Guides for Substrate Noise Reduction in CMOS Digital Circuits," IEEE J. Solid-State Circuits, Vol. 36 (2001), pp. 539-549.

[00-64] M. Nagata, T. Ohmoto, J. Nagai, T. Morie, and A. Iwata, "Test Circuits for Substrate Noise Evaluation in CMOS Digital ICs," Proc. of Asia and South Pacific Design Automation Conf. (ASP-DAC2001), pp. 13-14.

[00-65] Y. Murasaka, M. Nagata, T. Ohmoto, T. Morie, and A. Iwata, "Chip-Level Substrate Noise Analysis with Network Reduction by Fundamental Matrix Computation," Proc. of Int. Symp. Quality Electronic Design (ISQED2001), pp. 482-487.