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2006 (2006 April - 2007 March)

  1. Advanced device process and material technologies for ULSI
  2. Self assembling technique and quantum structure
  3. Technologies for intelligent systems

1. Advanced device, process, and material technologies for ULSI

  • Fabrication techniques for scaled MOS devices and TFTs
  • Evaluation and modeling techniques for scaled MOS devices
  • High-k dielectrics
  • Optical interconnection
  • Low-k dielectrics
  • Wireless interconnects
  • CVD and contamination/particle control

    • 1.1. Fabrication techniques for scaled MOS devices and TFTs

    1. K. Shibahara, “Metal Gate Technology for 45nm and beyond,” Proceedings of 2006 Int. Symp. on VLSI Technology, Systems, and Applications (VLSI-TSA 2006, Hsinchu, Taiwan, Apr. 24-26, 2006) pp. 105-106, Invited.
    2. K. Shibahara, A. Matsuno, M Hino, and K. Kurobe, “Mo Gate Deformation Induced by Laser Annealing Process,” Proceedings of 2006 Int. Symp. on VLSI Technology, Systems, and Applications (VLSI-TSA 2006, Hsinchu, Taiwan, Apr. 24-26, 2006) pp. 50-51.
    3. K. Shibahara, T. Eto, and K. Kurobe, “Merits of Heat-assist for Melt Laser Annealing,” IEEE Trans. Electron Devices, Vol. 53, No. 5, pp. 1059-1064, 2006.
    4. T. Fukunaga, K. Hosawa, T. Hosoi, and K. Shibahara, “Xe Preamorphization Implantation for Transient Enhanced Diffusion Suppression of As in Ge Substrate,” Ext. Int. Conf. on Solid State Devices and Materials (SSDM'06, Yokohama, Sep. 13-15, 2006) pp. 452-453.
    5. T. Hosoi, K. Sano, K. Hosawa, and K. Shibahara, “Pd2Si Fully-Silicided Gate: Kinetics of Silicide Formation and Workfunction Tuning,” Ext. Abs. Int. Conf. on Solid State Devices and Materials (SSDM'06, Yokohama, Sep. 13-15, 2006) pp. 218-219.
    6. A. Matsuno, and K. Shibahara, “Effects of Pulse Duration on the Formation of Ultra Shallow Junction Formed by an Excimer Laser Anneal Method,” Jpn. J. Appl. Phys., Vol. 45, No. 11A, pp. 8537-8541, 2006.
    7. K. Okuyama, K. Yoshikawa, and H. Sunami, “Characterization of Subthreshold Behavior of Narrow-Channel SOI nMOSFET with Additional Side-Gate Electrodes,” Ext. Abs. Int. Conf. on Solid State Devices and Materials (SSDM'06, Yokohama, Sep. 13-15, 2006) pp. 506-507.
    8. K. Kobayashi, K. Okuyama, and H. Sunami, “Plasma-Doping Induced Damages Associated with Source/Drain Formation in Beam-Channel MOS Transistor on 1-mm Thick SOI Substrate,” Abs. of 32nd Int. Conf. on Micro- and Nano-Engineering (Barcelona, Spain, Sept. 17-20, 2006) pp. 493-494.
    9. S. Matsumura, A. Sugimura, K. Okuyama, and H. Sunami, “Anomalous Whisker Generation in Ni-Silicided Source and Drain for Three-Dimensional Beam-Channel MOS Transistor on SOI Substrate,” Abs. of Advanced Metallization Conf. (Tokyo, Sept. 25-27, 2006) pp. 90-91.
    10. 角南英夫著,「VLSI工学－製造プロセス編－」（社)電子情報通信学会編、（株)コロナ社、2006年8月.
    11. M. Ooka and S. Yokoyama, “Effect of H2 Addition during Cu Thin Film Sputtering,” Jpn. J. Appl. Phys. Vol. 45, No. 12, pp. 9058-9062, 2006.
    12. M. Ooka and S. Yokoyama, “Effect of H2 Addition during Cu Thin Film Sputtering,” Proc. of Int. Symp. on VLSI Technology, System and Applications (VLSI-TSA 2006, Hsinchu, Taiwan, Apr. 24-26, 2006) pp. 127-128.
    13. H. Kaku, S. Higashi, T. Okada, H. Murakami, S. Miyazaki, “Correlation between Annealing Temperature and Crystallinity of Si Films Prepared by Thermal Plasma Jet Crystallization Technique,” Mater. Res. Soc. Symp. Proc. Vol.910 (San Francisco, U.S.A., April 17-21, 2006) pp. A21.18-1?A21.18-6.
    14. H. Kaku, S. Higashi, T. Okada, H. Murakami, and S. Miyazaki, “Direct Observation of Millisecond Phase Transformation in a-Si Films Induced by Thermal Plasma Jet Irradiation,” Abs. of Int. TFT Conf., 2006(Kitakyushu, Jan. 19-20, 2006) p. A21-18.
    15. T. Yorimoto, S. Higashi, H. Kaku, T. Okada, H. Murakami, S. Miyazaki, M. Maki and T. Sameshima, “Electrical Characteristics of Lightly-Doped Si Films Crystallized by Thermal Plasma Jet Irradiation,” Abs. of Material Research Society Japan (Tokyo, Dec. 8-10, 2006) H-22-M.
    16. T. Okada, S. Higashi, H. Kaku, T. Yorimoto, H. Murakami and S. Miyazaki, ”Growth of Si Crystalline in SiOx Films Induced by Millisecond Rapid Thermal Annealing Using Thermal Plasma Jet,” Proc. of the 3rd Int. TFT Conference (Rome, Italy, Jan. 25-26, 2007) pp. 82-85.
    17. T. Okada, S. Higashi, H. Kaku, N. Koba, H. Murakami and S. Miyazaki, ”Effect of He Addition on the Heating Characteristics of Substrate Surface Irradiated by Ar Thermal Plasma Jet,” Proc. of Int. Symp. on Dry Process (Aichi, Nov. 29-30, 2006) pp. 317-318.
    18. K. Sakaike, S. Higashi, H. Kaku, T. Sakata, H. Murakami and S. Miyazaki, “Semiconductor Diode Laser Annealing of Amorphous Ge Films,” 2nd Int. WorkShop on New Group IV Semiconductor Nanoelectronics (Sendai, Oct. 2- 3, 2006) pp. 65-66.
    19. T. Sakata, K. Makihara, S. Higashi and S. Miyazaki, “Formation of Highly-Crystallized Ge:H Films from VHF Inductively-Coupled Plasma of GeH4,” 2nd Int. WorkShop on New Group IV Semiconductor Nanoelectronics (Sendai, Oct. 2- 3, 2006) pp. 61-62.
    20. T. Okada, S. Higashi, N. Koba, H. Kaku, H. Murakami, S. Miyazaki, “Impact of He Addition on the Substrate Surface Temperature During Rapid Thermal Annealing Induced by Ar Thermal Plasma Jet Irradiation,” Abs. of 8th Int. Conf. on Advanced Surface Engineering (Tokyo, Apr. 25-16, 2006) p. 73.
    21. T. Okada, S. Higashi, H. Kaku, N. Koba, H. Murakami and S. Miyazaki, “Analysis of Transient Temperature Profile During Thermal Plasma Jet Annealing of Si Films on Quartz Substrate,” Jpn. J. Appl. Phys., Vol. 45 No. 5B, pp. 4355-4357, 2006.
    22. S. Higashi, H. Kaku, T. Okada, H. Murakami and S. Miyazaki, “Crystallization of Si in Millisecond Time Domain Induced by Thermal Plasma Jet Irradiation,” Jpn. J. Appl. Phys., Vol. 45 No. 5B, pp. 4313-4320, 2006.
    23. N. Kosku and S. Miyazaki, “The Application of very High Frequency Inductively-coupled Plasma to High-Rate Growth of Microcrystalline Silicon Films,” J. Non-Cryst. Solid, Vol. 352 No. 9-20, pp. 911-914, 2006.
    24. N. Kosku and S. Miyazaki, “Insights into the high-rate growth of highly crystallized silicon films from inductively coupled plasma of H2-diluted SiH4,” Thin Solid Films, Vol. 511-512 pp. 265-270, 2006.
    25. A. Yamashita, Y. Okamoto, S. Higashi, S. Miyazaki, H. Watakabe and T. Sameshima, “In-Situ Observation of Rapid Crystalline Growth Induced by Excimer Laser Irradiation to Ge/Si Stacked Structure,” Thin Solid Films, Vol. 508 No. 1-2, pp. 53-56, 2006.

    1.2. Evaluation and modeling techniques for scaled MOS devices

    1. H.J. Mattausch, M. Miyake, T. Yoshida, S. Hazama, D. Navarro, N. Sadachika, T. Ezaki, and M. Miura-Mattausch, “HiSIM2 Circuit Simulation: Solving the Speed versus Accuracy Crisis,” IEEE Circuits and Devices Magazine Vol. 22 No. 9, pp. 29-38, 2006.
    2. M. Miura-Mattausch, N. Sadachika, D. Navarro, G. Suzuki, Y. Takeda, M. Miyake, T. Warabino, Y. Mizukane, K. Machida, R. Inagaki, T. Ezaki, H.J. Mattausch, T. Ohguro, T. Iizuka, M. Taguchi, S. Kumashiro, and S. Miyamoto, “HiSIM2: Advanced MOSFET Model Valid for RF-Circuit Simulation,” IEEE Trans. on Electron Devices, Vol. 53, No. 9, pp. 1994-2007, 2006.
    3. D. Navarro, Y. Takeda, M. Miyake, N. Nakayama, K. Machida, T. Ezaki, H.J. Mattausch, and M. Miura-Mattausch, “A Carrier-Transit-Delay-Based Non-Quasi-Static MOSFET Model for Circuit Simulation and Its Application to Harmonic Distortion Analysis,” IEEE Trans. on Electron Devices, Vol. 53, No. 9, pp. 2025-2034, 2006.
    4. N. Sadachika, D. Kitamaru, Y. Uetsuji, D. Navarro, M. M. Yusoff, T. Ezaki, H.J. Mattausch, and M. Miura-Mattausch, “Completely Surface-Potential-Based Compact Model of the Fully-Depleted SOI-MOSFET Including Short-Channel Effects,” IEEE Trans. on Electron Devices, Vol. 53, No. 9, pp. 2017-2024, 2006.
    5. M. Miura-Mattausch, D. Navarro, N. Sadachika, G. Suzuki, Y. Takeda, M. Miyake, T. Warabino, K. Machida, T. Ezaki, H.J. Mattausch, T. Ohguro, T. Iizuka, M. Taguchi, S. Kumashiro, R. Inagaki, and S. Miyamoto, “Advanced Compact MOSFET Model HiSIM2 Based on Surface Potentials with a Minimum Number of Approximations,” Proceedings of the 2006 NIST Nanotechnology Conf. and Trade Show (NIST-Nanotech ’06, May 2006) pp. 638-643, Invited.
    6. T. Warabino, M. Miyake, N. Sadachika, D. Navarro, Y. Takeda, G. Suzuki, T. Ezaki, M. Miura-Mattausch, H.J. Mattausch, T. Ohguro, T. Iizuka, M. Taguchi, S. Kumashiro, and S. Miyamoto, “Analysis and Compact Modeling of MOSFET High-Frequency Noise,” Proceedings of the IEEE Int. Conf. on Simulation of Semiconductor Processes and Devices (SISPAD’06, Sept. 2006) pp. 158-161.
    7. N. Sadachika, D. Kitamaru, Y. Uetsuji, D. Navarro, M. M. Yusoff, T. Ezaki, H.J. Mattausch, M. Miura-Mattausch, and S. Baba, “HiSIM-SOI: Complete Surface-Potential-Based Fully-Depleted SOI-MOSFET Model for Circuit Simulation,” Proc. 2006 China-Ireland Int. Conf. on Information and Communication Technologies (CIICT’06, Oct. 2006) pp. 242-245.
    8. T. Ezaki, T. Warabino, M. Miyake, N. Sadachika, D. Navarro, H.J. Mattausch, M. Miura-Mattausch, T. Ohguro, T. Iizuka, M. Taguchi, S. Kumashiro, and S. Miyamoto, “Noise Modeling Based on Self-Consistent Surface-Potential Description for Advanced MOSFETs aiming at RF Applications,” Proceedings of the 8th Int. Conf. on Solid-State and Integrated-Circuit Technology (ICSICT’06, Oct. 2006) pp. 1264-1267, Invited.
    9. M. Miyake, N. Sadachika, D. Navarro, Y. Mizukane, T. Ezaki, M. Miura-Mattausch, H.J. Mattausch, T. Ohguro, T. Iizuka, M. Taguchi, S. Kumashiro, and S. Miyamoto, “Surface-Potential-Based MOS-Varactor Model for RF Applications,” Ext. Abs. Int. Conf. on Solid State Devices and Materials (SSDM'06, Yokohama, Sep. 13-15, 2006) pp. 1044-1045.
    10. T. Ezaki, G. Suzuki, K. Konno, O. Matsushima, Y. Mizukane, D. Navarro, M. Miyake, N. Sadachika, H.J. Mattausch, and M. Miura-Mattausch, “Physics-Based Photodiode Model Enabling Consistent Opto-Electronic Circuit Simulation,” Technical Digest of IEEE Int. Electron Devices Meeting (San Francisco, U.S.A., Dec. 11-13, 2006) pp. 187-190.
    11. H.J. Mattausch, N. Sadachika, M. Miyake, D. Navarro, T. Warabino, K. Matsumoto, T. Ezaki, M. Miura-Mattausch, T. Yoshida, R. Inagaki, Y. Furui, S. Hazama, T. Ohguro, T. Iizuka, M. Taguchi, S. Kumashiro, and S. Miyamoto, “HiSIM231: Toward Solving the Speed versus Accuracy Crisis in Circuit Simulation”, Proceedings of the Int. Workshop on Compact Modeling (IWCM‘06, Jan. 2007) pp. 93-96.
    12. S. Zhu, A. Nakajima, T. Ohashi, and H. Miyake, “Mechanism of Dynamic Bias Temperature Instability in P- and N- MOSFETs: the Effect of Pulse Waveform,” IEEE Trans. Electron Devices, Vol. 53, No. 8, pp. 1805-1814, 2006.
    13. Y. Yokoyama, S. Zhu, and A. Nakajima, “Atomic Layer Deposition of HfO2 using Hf[N(C2H5)2]4 and H2O,” Jpn. J. Appl. Phys., Vol. 45, No. 9A, pp. 7091-7093, 2006.
    14. S. Zhu, A. Nakajima, T. Ohashi, and H. Miyake, “Improvement of mobility and NBTI reliability in MOSFETs with ALD-Si-nitride/SiO2 stack dielectrics and p+-poly-Si gate,” Ext. Abs. Int. Conf. on Solid State Devices and Materials (SSDM'06, Yokohama, Sep. 13-15, 2006) pp. 420-421.
    15. S. Zhu, A. Nakajima, T. Ohashi, and H. Miyake, “Bias Temperature Instability in MOSFETs with Atomic-Layer-Deposited Si-Nitride/SiO2 Stack Gate Dielectrics,” 8th Int. Conf. on Solid State and Integrated-Circuit Technology (ICSICT2006, Shanghai, China, Oct. 23-26, 2006) pp.1126-1128.

    1.3. High-k dielectrics

    1. Y. Pei, A. Ohta, H. Murakami, S. Higashi, S. Miyazaki, T. Akasaka and Y. Nara, “Analysis of Leakage Current through Ultrathin HfSiOxN/SiO2 Stack Gate Dielectric Capacitors with TiN/W/TiN Gate,” Ext. Abs. of 2006 Int. Workshop on Dielectric Thin Films For Future ULSI Devices-Science and Technology (Kawasaki, Nov. 8-10, 2006) pp. 107-108.
    2. A. Ohta, S. Miyazaki, Y. Akasaka, H. Watanabe, K. Shiraishi, K. Yamada, S. Inumiya and Y. Nara, “A New Insight into Control of Fermi Level Pinning in TiN/HfSiON Gate Stack,” Ext. Abs. of 2006 Int. Workshop on Dielectric Thin Films For Future ULSI Devices-Science and Technology (Kawasaki, Nov. 8-10, 2006) pp. 61-62.
    3. A. Ohta, H. Nakagawa, H. Murakami, S. Higashi, S.Miyazaki, T. Kawahara, K. Torii and Y. Nara, “Characterization of Dielectric Stack Structures of Hafnium Silicate and Silicon Oxynitride formed on Si(100),” Ext. Abs. of 2006 Int. Workshop on Dielectric Thin Films For Future ULSI Devices-Science and Technology (Kawasaki, Nov. 8-10, 2006) pp. 31-32.
    4. H. Nakagawa, A. Ohta, H. Murakami, S. Higashi and S. Miyazaki, “Photoemission Study of HfO2/Ge(100) Stacked Structures,” Ext. Abs. of 2006 Int. Workshop on Dielectric Thin Films For Future ULSI Devices -Science and Technology (Kawasaki, Nov. 8-10, 2006) pp. 13-14.
    5. H. Nakagawa, A. Ohta, H. Murakami, S. Higashi and S. Miyazaki, “Characterization of Chemical Bonding Features of Silicon Oxynitride Films Formed on Ge(100) Surface,” 2nd Int. WorkShop on New Group IV Semiconductor Nanoelectronics (Sendai, Oct. 2-3, 2006) pp. 63-64.
    6. A. Ohta, H. Yoshinaga, H. Murakami, D. Azuma, Y. Munetaka, S. Higashi, S. Miyazaki, T. Aoyama, K. Kosaka and K. Shibahara, “Evaluation of Chemical Structures and Work Function of NiSi near the Interface between Nickel Silicide and SiO2,” Ext. Abs. Int. Conf. on Solid State Devices and Materials (SSDM'06, Yokohama, Sep. 13-15, 2006) pp. 216-217.
    7. S. Miyazaki, A. Ohta, Y. Pei, S. Inumiya and Y. Nara, “Influences of Nitrogen Incorporation on Electronic Structure and Electrical Properties of Ultrathin Hafnium Silicate,” The E-MRS 2006 Spring Meeting (Nice, France, May 29-Jun. 2, 2006) L-4a, Invited.
    8. S. Miyazaki, A. Ohta, Y. Pei, S. Inumiya, Y. Nara and K. Yamada, “Depth Profiling of Chemical and Electronic Structures and Defects of Ultrathin HfSiON on Si(100),” 210th Electrochemical Society Meeting (Cancun, Mexico, Oct. 29-Nov. 3, 2006) p. 1104, Invited.

    1.4. Optical interconnection

    1. Y. Tanushi and S. Yokoyama, “Design and Simulation of Ring Resonator Switches using Electro-Optic Materials,” Jpn. J. Appl. Phys. Vol. 45, No. 4B, pp. 3493-3497, 2006.
    2. M. Suzuki, Zhimou Xu, Y. Tanushi, and S. Yokoyama, “Structural and Optical Properties of Electro-Optic Material: Sputtered (Ba,Sr)TiO3,” Jpn. J. Appl. Phys., Vol. 45, No. 4B, pp. 3488-3492, 2006.
    3. Z. Xu, M. Suzuki, Y. Tanushi, K. Wakushima, and S. Yokoyama, “Groove-Buried Optical Waveguides Based on Metal Organic Solution-Derived Ba0.7Sr0.3TiO3 Thin Films,” Jpn. J. Appl. Phys., Vol. 45, No. 4B, pp. 3482-3487 ,2006.
    4. T. Tabei, K. Maeda, S. Yokoyama, and H. Sunami, “Fabrication of spin-coat optical waveguides for optically interconnected LSI and influence of fabrication process on lower layer MOS capacitors,” Jpn. J. Appl. Phys. Vol. 45, No. 4B, pp. 3498-3503, 2006.
    5. Z. Xu, M. Suzuki, Y. Tanushi, and S. Yokoyama, “Monolithically integrated optical modulator based on polycrystalline Ba0.7Sr0.3TiO3 thin films,” Appl. Phys. Lett., Vol. 88, No. 16, pp. 161107-1?161107-3, 2006.
    6. Z. Xu, Y. Tanushi, M. Suzuki, K. Wakushima, and S. Yokoyama, “Optical properties of amorphous Ba0.7Sr0.3TiO3 thin films obtained by metal organic decomposition technique,” Thin Solid Films, Vol. 515, pp. 2326-2331, 2006.
    7. M. Suzuki, K. Nagata, Y. Tanushi, and S. Yokoyama, “Low Temperature Fabrication of Monolithic Mach-Zehnder Optical Modulator on Silicon using Sputtered (Ba,Sr)TiO3 and Mechanism of Transient Response,” Ext. Abs. Int. Conf. on Solid State Devices and Materials (SSDM'06, Yokohama, Sep. 13-15, 2006) pp. 48-49.
    8. Y. Tanushi and S. Yokoyama, “Compact Multi-Mode Optical Ring Resonators for Interconnection on Si Chips,” Ext. Abs. Int. Conf. on Solid State Devices and Materials (SSDM'06, Yokohama, Sep. 13-15, 2006) pp. 44-45.

    1.5. Low-k dielectrics

    1. A. Ishikawa, Y. Shishida, T. Yamanishi, N. Hata, T. Nakayama, N. Fujii, H. Tanaka, H. Matsuo, K. Kinoshita, and T. Kikkawa, “Influence of CMP Chemicals on the Properties of Porous Silica Low-k Films,” J. Electrochem. Soc. Vol. 153, No. 7, pp. G692-G696, 2006.
    2. S. Kuroki and T. Kikkawa, “Measurement and Analysis of Water Adsorption in Porous Silica Films,” J. Electrochem. Soc., Vol. 153, No. 8, pp. G759-G764, 2006.
    3. M. Shimoyama, R. Yagi, S. Chikaki, N. Fujii, T. Nakayama, K. Kohmura, H. Tanaka, K. Kinoshita, and T. Kikkawa, “Influence of Cu Electroplating Solution on Self-Assembled Porous Silica Low-k Films,” J. Electrochem. Soc. Vol. 153, No. 8, pp. G870-G873, 2006.
    4. T. Ono, K. Kinoshita, H. Takahashi, N. Fujii, Y. Sonoda, Y. Oku, K. Kohmura, R. Yagi, N. Hata, and T. Kikkawa, “Recovery from Plasma-Process-Induced Damage in Porous Silica low-k Films by Organosiloxane Vapor Annealing,” Jap. J. Appl. Phys., Vol. 45, No. 8A, pp. 6231-6235, 2006.
    5. S. Takada, N. Hata, X. Li, N. Fujii, T. Nakayama, and T. Kikkawa, “Nondestructive Characterization of Temperature-Dependent Backbone Si-O-Si Structure in Porous Silica Films by in-situ Fourier-Transform Infrared Spectroscopy,” Ext. Abs. Int. Conf. on Solid State Devices and Materials (SSDM'06, Yokohama, Sep. 13-15, 2006) pp. 154-155.
    6. T. Seo, T. Yoshino, N. Hata, and T. Kikkawa, “Formation of Mesoporous Pure Silica Zeolite Film,” Ext. Abs. Int. Conf. on Solid State Devices and Materials (SSDM'06, Yokohama, Sep. 13-15, 2006) pp. 462-463.
    7. Y. Cho, K. Kohmura, and T. Kikkawa, “Pure-Silica Zeolite Films Prepared by a Vapor Phase Transport Method,” Ext. Abs. Int. Conf. on Solid State Devices and Materials (SSDM'06, Yokohama, Sep. 13-15, 2006) pp. 464-465.
    8. M. Yamaji, N. Hata, T. Nakayama, Y. Shishida, Y. Hyoudo, and T. Kikkawa, “The Structural Origin of Determining the Coefficient of Thermal Expansion for Porous Silica Low-k Films,” Ext. Abs. Int. Conf. on Solid State Devices and Materials (SSDM'06, Yokohama, Sep. 13-15, 2006) pp. 1010-1011.
    9. Y. Kayaba, K. Kohmura, and T. Kikkawa, “Ionic Conduction Leakage Current in Porous Silica Films,” Ext. Abs. Int. Conf. on Solid State Devices and Materials (SSDM'06, Yokohama, Sep. 13-15, 2006) pp. 1018-1019.
    10. T. Takimura, N. Hata, Y. Shishida, S. Chikaki, and T. Kikkawa, “Nondestructive Characterization of Dielectric Stack Structures by Laser-Pulse-Generated Surface Acoustic Wave Analysis,” Ext. Abs. Int. Conf. on Solid State Devices and Materials (SSDM'06, Yokohama, Sep. 13-15, 2006) pp. 1024-1025.
    11. T. Yoshino, J. Kawahara, N. Hata, Y. Shishida, and T. Kikkawa, “Plasma-Enhanced Polymerization Thin Films as a Drift Barrier for Cu Interconnects,” Ext. Abs. Int. Conf. on Solid State Devices and Materials (SSDM'06, Yokohama, Sep. 13-15, 2006) pp. 1038-1039.
    12. T. Ono, H. Takahashi, K. Kinoshita, N. Fujii, N. Hata, and T. Kikkawa, “Plasma Etch Rates of Porous Silica Low-k Films with Different Dielectric Constants,” Jpn. J. Appl. Phys., Vol. 45, No. 11, pp. 8873-8875, 2006.
    13. T. Syozo, H. Nobuhiro, S. Yutaka, F. Nobutoshi, and T. Kikkawa, “Dependences of Young’s Modulus of Porous Silica Low Dielectric Constant Films on Skeletal Structure and Porosity,” J. Appl. Phys., Vol. 100, pp. 123512-1?123512-5, 2006.
    14. K. Kurihara, T. Ono, K. Kohmura, H. Tanaka, N. Fujii, N. Hata, T. Kikkawa, “Carbon Loss Induced by Plasma Beam Irradiation in Porous Silica Films,” J. Appl. Phys., Vol. 101 Issue 11, pp. 113301?113301-6, 2007.
    15. J. Kawahara, N. Kunimi, K. Kinoshita, A. Nakano, M. Komatsu, Y. Seino, and T. Kikkawa, “An Organic Low-k Film Deposited by Plasma-Enhanced Copolymerization,” J. Electrochem. Soc. Vol. 154, Issue 3, pp. H147-H152, 2007.
    16. J. Kawahara, N. Kunimi, A. Nakano, K. Kinoshita, Y. Hayashi, M. Komatsu, Y. Seino, R. Ichikawa, Y. Takasu, and T. Kikkawa, “Effect of Bridging Groups of Precursors on Modulus Improvement in Plasma-Enhanced Copolymerized Low-k Films,” J. Electrochem. Soc. Vol. 154, Issue 3, pp. H198-H201, 2007.

    1.6. Wireless interconnects

    1. K. Kimoto, N. Sasaki, P. K. Saha, M. Nitta, T. Kikkawa and M. Sasaki, “Analysis of Transmission Characteristics of Gaussian Monocycle Pulse for Silicon Integrated Antennas,” Jpn. J. of Appl. Phys., Vol. 45, No. 4B, pp.3272-3278, 2006.
    2. P. K. Saha, N. Sasaki, K. Kimoto, and T. Kikkawa, “A 2.4 GHz Differential Wavelet Generator in 0.18 μm Complementary Metal-Oxide-Semiconductor for 1.4 Gbps Ulatra-Wideband Impulse Radio in Wireless Inter/Intra-Chip Data Communication,” Jpn. J. of Appl. Phys., Vol. 45, No. 4B, pp. 3279-3285, 2006.
    3. K. Kimoto and T. Kikkawa, “Signal Transmission Characteristics between Si Chips with Air Gap using Si Integrated Dipole Antennas,” Jpn. J. of Appl. Phys., Vol. 45, No. 6A, pp. 4968-4976, 2006.
    4. P. K. Saha, N. Sasaki and T. Kikkawa, “A Single-chip Gaussian Monocycle Pulse Transmitter using 0.18 μm CMOS Technology for Intra/Interchip UWB Communication,” 2006 Symp. on VLSI Circuits Digest of Technical Papers (Honolulu, U.S.A., June 15-17, 2006) pp. 252-253.
    5. M. Nitta, K. Kimoto, N. Sasaki and T. Kikkawa, “Influence of WLAN on Inter-chip UWB Signal Transmission with Si Integrated Antennas,” Proc. of IEEE Int. Symp. on Antennas and Propagation with USNC/URSI National Radio Science and AMEREM Meetings, Vol.2, pp. 917-920, July 2006.
    6. K. Kimoto, N. Sasaki, P. K. Saha, M. Nitta and T. Kikkawa, “Analysis of Si Integrated Dipole Antennas for Ultrawideband Signal Transmission,” Proc. of IEEE Int. Symp. on Antennas and Propagation with USNC/URSI National Radio Science and AMEREM Meetings, Vol.5, pp. 4661-4664, July 2006.
    7. K. Kimoto, N. Sasaki, M. Nitta, M. Fukuda and T. Kikkawa, “Inter-chip Transmission Characteristics of Meander Dipole Antennas Integrated in 0.18 μm CMOS UWB Transceiver Chips,” Ext. Abs. Int. Conf. on Solid State Devices and Materials (SSDM'06, Yokohama, Sep. 13-15, 2006) pp. 66-67.
    8. N. Sasaki, M. Fukuda, M. Nitta, K. Kimoto and T. Kikkawa, “A Single-chip Ultra-Wideband Receiver using Silicon Integrated Antennas for Inter-chip Wireless Interconnection,” Ext. Abs. Int. Conf. on Solid State Devices and Materials (SSDM'06, Yokohama, Sep. 13-15, 2006) pp. 70-71.
    9. M. Fukuda, P. K. Saha, N. Sasaki, and T. Kikkawa, “A 0.18 μm CMOS Impulse Radio Based UWB Transmitter for Global Wireless Interconnections of 3D Stacked-Chip System,” Ext. Abs. Int. Conf. on Solid State Devices and Materials (SSDM'06, Yokohama, Sep. 13-15, 2006) pp.72-73.

    1.7. CVD and contamination/particle control

    1. M. Shimada, Y. Azuma K. Okuyama, Y. Hayashi and E. Tanabe, “Plasma Synthesis of Light Emitting Gallium Nitride Nanoparticles Using a Novel Microwave-resonant Cavity,” Jpn. J. Appl. Phys., Vol. 45, No. 1A, pp. 328-332, 2006.
    2. C. S. Kim, L. Bao, K. Okuyama, M. Shimada and H. Niinuma, “Filtration Efficiency of a Fibrous Filter for Nanoparticles,” J. Nanoparticle Res., Vol. 8, No. 2, pp. 215-221, 2006.
    3. D. K. Song, H. M. Lee, H. Chang, S. S. Kim, M. Shimada and K. Okuyama, “Performance Evaluation of Long Differential Mobility Analyzer (LDMA) in Measurements of Nanoparticles,” J. Aerosol Sci., Vol. 37, No. 5, pp. 598-615, 2006.
    4. N. Kashihara, H. Setyawan, M. Shimada, Y. Hayashi, C. S. Kim, K. Okuyama and S. Winardi, “Suppression of Particle Generation in a Plasma Process Using a Sine-wave Modulated rf Plasma,” J. Nanoparticle Res., Vol. 8, No. 3-4, pp. 395-403, 2006.
    5. M. Shimada, K. Okuyama and Y. Hayashi, “Observation of Particle Behavior in a PECVD Reactor Using an in situ Visualization System,” Proc. of The Seventh Int. Aerosol Conf., Vol. 1, pp. 564-565, 2006.

    2. Self-assembling techniques and quantum structures

    2.1. Silicon quantum dots and quantum electronics

    1. K Makihara, Y. Kawaguchi, H. Murakami, S. Higashi, S. Miyazaki, “Characterization of Electronic Charged States of Impurity Doped Si Quantum Dots Using AFM/Kelvin Probe Technique,” Abs. of IUMRS-ICA-2006 (Cheju, Korea, Sep. 10-14, 2006) p. 82.
    2. K. Makihara, Y. Kawaguchi, M. Ieda, H. Murakami,S. Higashi, S. Miyazaki, “Phosphorus Doping to Si Quantum Dots and Its Floating Gate Application,” Abs. of 2006 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices (Sendai, Jul. 3-5, 2006) pp. 135-138.
    3. K. Makihara, T. Nagai, M. Ikeda, Y. Kawaguchi, H. Murakami, S. Higashi, S. Miyazaki, , “Charging and Discharging Characteristics of P-doped Si Quantum Dots Floating Gate,” Abs. of The 2006 Int. Meeting for Future of Electron Devices, Kansai (IMFEDK2006, Kyoto, Apr. 24-26, 2006) pp. 67-68.
    4. K. Makihara, M. Ikeda, S. Higashi and S. Miyazaki, “Study of Charged states of Si Quantum Dots with Ge Core,” 210th Electrochemical Society Meeting (Cancun, Mexico, Oct. 29-Nov. 3, 2006) p. 1425.
    5. S. Miyazaki, K. Makihara, M. Ikeda, “Characterization of Electronic Charged States of Si-based Quantum Dots for Multi-valued MOS Memories,” Proceedings of The 8th Int. Conf. on Solid-State and Integrated-Circuit Technology (Shanghai, China, Oct. 23-26, 2006) pp. 736-739 Invited.
    6. S. Miyazaki, K. Makihara and M. Ikeda, “Control of Electronic Charged States of Si-based Quantum Dots for Floating Gate Aplication,” 2nd Int. WorkShop on New Group IV Semiconductor Nanoelectronics (Sendai, Oct. 2-3, 2006) pp. 49-50, Invited.
    7. S. Miyazaki, M. Ikeda and K. Makihara, “Characterization of Electronic Charged States of Si-Based Quantum Dots and Their Application to Floating Gate Memories,” 209th Electrochemical Society Meeting (Denver, Colorado, May 7-12, 2006) p. 390 , Invited.
    8. K. Makihara, M. Ikeda, S. Higashi and S. Miyazaki, “Study of Charged States of Si Quantum Dots with Ge Core,” ECS Trans., Vol. 3 Iss. 7 pp. 257-263, 2006.
    9. S. Miyazaki, A. Ohta, S. Inumiya, Y. Nara and K. Yamada, “Depth Profiling of Chemical and Electronic Structures and Defects of Ultrathin HfSiON on Si(100),” ECS Trans., Vol. 3 Iss. 3, pp. 171-180, 2006.
    10. S. Miyazaki, M. Ikeda and K. Makihara, “Characterization of Electronic Charged States of Si-Based Quantum Dots and Their Application to Floating Gate Memories,” ECS Trans., Vol. 2 Iss. 1, p. 157-164, 2006.
    11. J. Nishitani, K. Makihara, M. Ikeda, H. Murakami, S. Higashi and S. Miyazaki, “Decay Characteristics of Electronic Charged States of Si Quantum Dots as Evaluated by an AFM/Kelvin Probe Technique,” Thin Solid Films, Vol. 508 No. 1-2, pp. 190-194, 2006.
    12. K. Makihara, J. Xu, M. Ikeda, H. Murakami, S. Higashi and S. Miyazaki, “Characterization of Electronic Charged States of P-doped Si Quantum Dots Using AFM/Kelvin Probe,” Thin Solid Films, Vol. 508 No. 1-2, pp. 186-189, 2006.

    2.2. Single electron transistors

    1. K. Ohkura, T. Kitade, and A. Nakajima, “Cotunneling current in Si single-electron transistor based on multiple islands,” Appl. Phys. Lett., Vol. 89, No.18, pp. 183520-1?183520-3, 2006.
    2. K. Ohkura, T. Kitade, and A. Nakajima, “Cotunneling Current in Si Single-Electron Transistor Based on Multiple Islands,” 2006 Int. Microprocesses and Nanotechnology Conf. (MNC 2006, Kamakura, October 24-27, 2006) pp. 166-167.

    3. Technologies for intelligent systems

    1. K. Tanigawa, T. Hironaka, M. Maeda, T. Sueyoshi, K. Aoyama, T. Koide and H.J. Mattausch, “Performance Evaluation of Superscalar Processor with Multi-Bank Register File and an Implementation Result, ” WSEAS Transactions on Computer, Vol. 5, Iss. 9, pp. 1993-2000, 2006.
    2. H. Noda, K. Dosaka, H.J. Mattausch, T. Koide, F. Morishita, and K. Arimoto, “A Reliability-Enhanced TCAM Architecture with Associated Embedded DRAM and ECC,” IEICE Trans. on Electronics, Vol. E89-C, No. 11, pp. 1612-1619, 2006.
    3. T. Kumaki, Y. Kuroda, M. Ishizaki, T. Koide, H.J. Mattausch, H. Noda, K. Dosaka, K. Arimoto, and K. Saito, “Real-Time Huffman Encoder with Pipelined CAM-Based Data Path and Code-Word-Table Optimizer”, IEICE Trans. on Information & Systems, Vol. E90-D, No. 1, pp. 334-345, 2007.
    4. T. Kumaki, Y. Kono, M. Ishizaki, T. Koide, and H.J. Mattausch, “Scalable FPGA/ASIC Implementation Architecture for Parallel Table-lookup Coding Using Multi-ported Content Addressable Memory,” IEICE Trans. on Information & Systems, Vol. E90-D, No. 1, pp. 346-354, 2007.
    5. K. Johguchi, Y. Mukuda, K. Aoyama, H.J. Mattausch, and T. Koide, “A 2-stage-pipelined 16 Port SRAM with 590 Gbps Random Access Bandwidth and Large Noise Margin,” IEICE Electronics Express, Vol. 4, No. 2, pp. 21-25, 2007.
    6. K. Yamaoka, T. Morimoto, H. Adachi, K. Awane, T. Koide, and H.J. Mattausch, “Multi-Object Tracking VLSI Architecture using Image-Scan based Region Growing and Feature Matching,” Proc. IEEE Int. Symp. on Circuits and Systems (ISCAS’06, May 2006) pp. 5575-5578.
    7. Md. A. Abedin, K. Kamimura, A. Ahmadi, T. Koide and H.J. Mattausch, “Minimum Euclidean Distance Associative Memory Architecture with Fully-Parallel Search Capability,” 13th Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI06, Apr. 2006) pp. 350-354.
    8. A. Ahmadi, M. A. Ritonga, Md. A. Abedin, H.J. Mattausch, and T. Koide, “A Learning OCR System Using Short/Long-term Memory Approach and Hardware Implementation in FPGA,” Proceedings of the 2006 IEEE Congress on Evolutionary Computation (WCCI‘2006, Jul. 2006) pp. 2702-2708.
    9. K. Tanigawa, T. Hironaka, M. Maeda, T. Sueyoshi, K. Aoyama, T. Koide and H.J. Mattausch, “Performance Evaluation of Superscalar Processor with Multi-Bank Register File Using SPEC2000,” Proceedings of the 10th WSEAS Int. Conf. on COMPUTERS (Jul. 2006) pp. 1062-1067.
    10. K. Johguchi, K. Aoyama, T. Sueyoshi, H.J. Mattausch, T. Koide, M. Maeda, T. Hironaka, and K. Tanigawa, “Multi-Bank Register File for Increased Performance of Highly-Parallel Processors,” Proceedings of the 32nd European Solid-State Circuits Conference (ESSCIRC‘06, Montreux, Switzerland, Sep. 18-22, 2006) pp. 154-157.
    11. Md. A. Abedin, Y. Tanaka, A. Ahmadi, T. Koide and H.J. Mattausch, “Nearest Euclidean-Distance-Search Associative Memory Architecture with Fully Parallel Mixed Digital-Analog Match Circuitry”, Ext. Abs. Int. Conf. on Solid State Devices and Materials (SSDM'06, Yokohama, Sep. 13-15, 2006) pp. 282-283.
    12. T. Morimoto, H. Adachi, K. Yamaoka, K. Awane, T. Koide and H.J. Mattausch, “Image-Scan Video Segmentation Architecture and FPGA Implementation,” Ext. Abs. Int. Conf. on Solid State Devices and Materials (SSDM'06, Yokohama, Sep. 13-15, 2006) pp. 590-591.
    13. Md. A. Abedin, Y. Tanaka, A. Ahmadi, T. Koide and H.J. Mattausch, “Fully Parallel Associative Memory Architecture with Mixed Digital-Analog Match Circuit for Nearest Euclidean Distance Search,” Proc. of the IEEE Asia Pacific Conf. on Circuits and Systems (APCCAS’06, Dec. 2006) pp. 1311-1314.
    14. T. Morimoto, H. Adachi, K. Yamaoka, T. Koide and H.J. Mattausch, “An FPGA-Based Region-Growing Video Segmentation System with Boundary-Scan-Only LSI Architecture,” Proc. of the IEEE Asia Pacific Conf. on Circuits and Systems (APCCAS’06, Dec. 2006) pp. 946-949.
    15. T. Kumaki, Y. Kouno, M. Ishizaki, T. Koide, H.J. Mattausch, “Application of Multi-ported CAM for Parallel Coding,” Proc. of the IEEE Asia Pacific Conf. on Circuits and Systems (APCCAS’06, Dec. 2006) pp. 1681-1684.
    16. K. Johguchi, Z. Zhu, H.J. Mattausch, T. Koide, T. Hironaka, and K. Tanigawa, “Unified Data/Instruction Cache with Hierarchical Multi-Port Architecture and Hidden Precharge Pipeline,” Proc. of the IEEE Asia Pacific Conf. on Circuits and Systems (APCCAS’06, Dec. 2006) pp. 1299-1302.
    17. M. Ishizaki, T. Kumaki, Y. Kouno, T. Koide, H.J. Mattausch, Y. Kuroda, T. Gyoten, H. Noda, K. Dosaka, K. Arimoto and K. Saito, “Huffman Encoding Architecture with Self-Optimizing Performance and Multiple CAM-Match Utilization,” Proc. of the IEEE TENCON (TENCON’06, Nov. 2006) No. CA2.3.
    18. Y. Mukuda, K. Aoyama, K. Johguchi, H.J. Mattausch, T. Koide, M. Maeda, T. Hironaka, and K. Tanigawa, “Access Queues for Multi-Bank Register Files Enabling Enhanced Performance of Highly Parallel Processors,” Proc. of the IEEE TENCON (TENCON’06, Nov. 2006) No. CA2.4.
    19. T. Yoshimura and A. Iwata,“A Study of Interference in Synchronous Systems,” IEEE Trans. on Circuits and Systems, Vol.53, No. 8, pp. 1726-1740, 2006.
    20. M. Hori, M, Ueda and A. Iwata, “Stochastic Computing Chip for Measurement of Manhattan Distance,” Jpn. J. of Appl. Phys., Vol. 45, No. 4B, pp. 3301-3306, 2006.
    21. M. Sasaki, M. Shiozaki, A. Mori, A. Iwata, and H. Ikeda, “17GHz Fine Grid Clock Distribution with Uniform-Amplitude Standing-Wave Oscillator,” 2006 Symp. on VLSI Circuits Digest of Technical Papers (Honolulu, U.S.A., June 15-17, 2006) pp. 124-125.
    22. K. Sasaki, T. Morie, and A. Iwata, “A VLSI Spiking Feedback Neural Network with Negative Thresholding and Its Application to Associative Memory,” IEICE Trans. Electron., Vol. E89-C, No. 11, pp. 1637-1644, 2006.
    23. M. Shiozaki, M. Sasaki, A. Mori, A. Iwata, and H. Ikeda, “20GHz Uniform-Phase Uniform-Amplitude Standing-Wave Clock Distribution,” IEICE Electronics Express (ELEX) Vol. 3, No. 2, pp. 11-16, 2006.
    24. M. Sasaki, “Design of a Millimeter-Wave CMOS Radiation Oscillator With an Above-Chip Patch Antenna,” IEEE Trans. Circuits Syst. II, Vol.53, No.10, pp. 1128-1132, 2006.
    25. T. Yoshida, Y. Masui, T. Mashimo, M. Sasaki and A. Iwata, “A 1 V Low-Noise CMOS Amplifier Using Autozeroing and Chopper Stabilization Technique,” IEICE Trans. Electrons., Vol. E89-C, pp. 769-774, .2006.
    26. D. Kosaka, M. Nagata, Y. Murasaka, and A. Iwata, “Evaluation of Isolation Structures against High-Frequency Substrate Coupling in Analog/Mixed-Signal Integrated Circuits,” IEICE Trans. Electron., Vol. E90-A, No. 2, pp. 380-387, 2007.
    27. M. Sasaki, M. Shiozaki, A. Mori, A. Iwata, and H. Ikeda, “12GHz Low-Area-Overhead Standing-Wave Clock Distribution with Inductively-Loaded and Coupled Technique,” IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC, San Francisco, U.S.A., Feb. 11-15, 2007) pp. 180-181.
    28. T. Sato, A. Inoue, T. Shiota, T. Inoue, Y. Kawabe, T. Hashimoto, T.Imamura,Y. Murasaka, M. Nagata,and A. Iwata, “On-Die Supply-Voltage Noise Sensor with Real-Time Sampling Mode for Low-Power Processor Application,” IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC, San Francisco, U.S.A., Feb. 11-15, 2007) pp.290-291.