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2003 (2003 April - 2004 March)
- Advanced device process and material technologies for ULSI
- Self assembling technique and quantum structure
- Technologies for intelligent systems
1. Advanced device, process, and material technologies for ULSI
- Fabrication techniques for scaled MOS devices
- Evaluation and modeling techniques for scaled MOS devices
- High-k dielectrics
- Interconnect technologies
- Low-k interlayer dielectrics
- Wireless interconnect technologies
- CVD and contamination/particle control
- Atomic scale processes
1.1 Fabrication techniques for scaled MOS devices
[03-1] K. Kurobe, Y. Ishikawa, K. Kagawa, Y. Niwatsukino, A. Matusno, and K. Shibahara, "Defects improvement and sheet resistance reduction in ultra shallow Sb+ implanted layers by multi-pulse KrF-excimer-laser annealing," Extend. Abst. Fabrication, Characterization, and Modeling of Ultra-Shallow Doping Profiles in Semiconductors (USJ 2003), pp. 98-103, 2003.
[03-2] K. Imai, S. Maruyama, T. Suzuki, T. Kudo, S. Miyake, M. Ikeda, T. Abe, S. Masuda, A. Tanabe, J.-W. Lee, K. Shibahara, S. Yokoyama, and H. Ooka, "60-nm Gate Length SOI CMOS Technology Optimized for System-on-a-SOI-Chip Solution," Proc. of the 203rd Meeting of Electrochemical Society, Silicon-on-insulator Technology and Devices XI, pp. 149-158, 2003.
[03-3] K. Imai, S. Shishiguchi, K. Shibahara, and S. Yokoyama, "Phosphorus-Assisted Low-Energy Arsenic Implantation Technology for N-Channel Metal-Oxide-Semiconductor Field-Effect Transistor Source/Drain Formation Process," Jpn. J. Appl. Phys., Vol. 42, No. 5A, pp. 2654-2659, 2003.
[03-4] M. Hino, T. Amada, N. Maeda, and K. Shibahara, "Influence of Nitrogen Profile on Metal Workfunction in Mo/SiO2/Si MOS Structure," Ext. Abst. Int. Conf. on Solid State Devices and Materials, pp. 494-495, Tokyo, Sept. 16-18, 2003.
[03-5] M. Murakawa, K. Shibahara, Y. Oda, T. Higuchi, and K. Nishi, "Ultra-shallow Boron Profile Fitting Compensating for Surface Contamination by Utilizing Genetic Algorithms," Ext. Abst. Int. Conf. on Solid State Devices and Materials, pp. 504-505, Tokyo, Sept. 16-18, 2003.
[03-6] K. Shibahara, K. Kurobe, Y. Ishikawa, K. Kagawa, Y. Niwatsukino, and A. Matsuno, "KrF Excimer Laser Annealing For Ultra Shallow Junction Formation: Approach For Irradiation Energy Density Reduction (Invited)," Extend. Abst. 11th Int. Conf. on Adv. Thermal Processing of Semiconductors (RTP 2003), pp. 13-16, 2003.
[03-7] S. Nakamura, M. Itano, H. Aoyama, K. Shibahara, S. Yokoyama, and M. Hirose, "Comparative Studies of Perfluorocarbon Alternative Gas Plasmas for Contact Hole Etch," Jpn. J. Appl. Phys., Vol. 42, No. 9A, pp. 5759-5764, 2003.
[03-8] M. Shibahara, S. Kotake, T. Inoue, A. Matsuno, K. Kagawa, and K. Shibahara, "Molecular Dynamics Simulation On Excimer Laser Annealing Process For Ultra Shallow Junction Formation," The 1st Int. Symp. on Micro & Nano Technology, pp. VIII-1-02-1-VIII-1-02-5, 2004.
[03-9] M. Ooka and S. Yokoyama, "Excellent Contact-Hole Etching with NH3 Added C5F8 Pulse-Modulated Plasma," Ext. Abst. Int. Conf. on Solid State Devices and Materials, pp. 454-455, Tokyo, Sept. 16-18, 2003.
[03-10] T. Furukawa, ,H. Yamashita, and H. Sunami, "A Proposal of Corrugated-Channel Transistor (CCT) with Vertically-Formed Channels for Area-Conscious Applications," Jpn. J. Appl. Phys., Vol. 42, Part 1, No. 4B, pp. 2067-2072, 2003.
[03-11] A. Takase, T. Kidera, and H. Sunami, "Field-Shield Trench Isolation with Self-Aligned Field Oxide," Jpn. J. Appl. Phys., Vol. 42, Part 1, No. 4B, pp. 2100-2105, 2003.
[03-12] 角南英夫, "ULSIの将来展望と高分子材料への期待," 高分子, 第52巻, 8月号, pp. 546-550, 2003.
[03-13] H. Sunami, T. Furukawa, and T. Masuda, "A Three-Dimensional MOS Transistor Formation Technique with Crystallographic Orientation-Dependent TMAH Etchant," SENSORS and ACTUATORS A: PHYSICAL, A111, pp. 310-316, 2004.
[03-14] A. Katakami, K. Kobayashi, and H. Sunami, "High-Aspect Ratio gate Formation of Beam-Channel MOS Transistor with Impurity-Enhanced oxidation of Silicon Gate," Ext. Abst. Int. Conf. on Solid State Devices and Materials, pp. 282-283, Tokyo, Sept. 16-18, 2003.
1.2 Evaluation and modeling techniques for scaled MOS devices
[03-15] T. Mizoguchi, H.J. Mattausch, H. Ueno, D. Kitamaru, K. Hisamitsu, M. Miura-Mattausch, S. Itoh, and K. Morikawa, "Extraction of Inter-and Intra-Chip Device-Parameter Variations with a Differential-Amplifier-Stage Test Circuit," Proc. of the 11th Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI’2003), pp. 76-82, Hiroshima, April 3, 2003.
[03-16] N. Nakayama, H. Ueno, T. Inoue, T. Isa, M. Tanaka, and M. Miura-Mattausch, "A Self-consistent Non-Quasi static MOSFET model for circuit simulation based on transient carrier response," J. Appl. Phys., Vol. 42, No. 4B, pp. 2132-2136, 2003.
[03-17] M. Miura-Mattausch, H. Ueno, H. J. Mattausch, K. Morikawa, S. Itoh, A. Kobayashi, and H. Masuda, "100nm-MOSFET Model for Circuit Simulation: Challenges and Solutions (Invited)," IEICE Transactions on Electronics, E86-C[6], pp. 1009-1021, 2003.
[03-18] O. Matsushima, M. Tanaka, H. Ueno, K. Hara, K. Konno, and M. Miura-Mattausch, "Carrier Transport in Highly Generated Carrier Concentration," Proc. Int. Conf. Nonequilibrium Carrier Dynamics in Semiconductors, pp. PTu4-8, July, 2003.
[03-19] S. Hosokawa, Y. Shiraga, H. Ueno, M. Miura-Mattausch, H. J. Mattausch, T. Ohguro, S. Kumashiro, M. Taguchi, H. Masuda, and S. Miyamoto, "Origin of Enhanced Thermal Noise for 100nm-MOSFETs," Ext. Abst. Int. Conf. on Solid State Devices and Materials, pp. 20-21, Tokyo, Sept. 16-18, 2003.
[03-20] D. Kitamaru, Y. Uetsuji, and M. Miura-Mattausch, "A Complete Surface-Potential-Based SOI-MOSFET Model for Circuit Simulation," Ext. Abst. Int. Conf. on Solid State Devices and Materials, pp. 622-623, Tokyo, Sept. 16-18, 2003.
[03-21] H. Ueno, S. Matsumoto, S. Hosokawa, M. Miura-Mattausch, H. J. Mattausch, S. Kumashiro, T. Yamaguchi, K. Yamashita, and N. Nakayama, "Modeling of 1/f Noise with HiSIM for 100nm CINS Technology," Proc. On the 1st International Workshop on Compact Modeling, pp. 18-23. Jan., 2004.
[03-22] M. Miura-Mattausch, "MOSFET Modeling for RF-CMOS Design (Invited)," Proc. Asia and South Pacific Design Automation Conference 2004, 6A-1, pp. 482-490. Jan., 2004.
[03-23] N. Nakayama, D. Navarro, M. Tanaka, H. Ueno, M. Miura-Mattausch, H. J. Mattausch, T. Ohguro, S. Kumashiro, M. Taguchi, T. Kage, and S. Miyamoto, "Non-quasi-static model for MOSFET based on carrier-transit delay," IEE Electronics Letters, Vol.40, No. 4, pp. 276-279. 2004.
[03-24] M. Miura-Mattausch, S. Hosokawa, D. Navarro, S. Matsumoto, H. Ueno, H. J. Mattausch, T. Ohguro, T. Iizuka, T. Taguchi, and S. Miyamoto, "Noise Modeling with HiSIM Based on Self-Consistent Surface-Potential Description (Invited)," Nanotech 2004 Conference Technical Proc., Vol. 2. pp. 66-69. March, 2004.
[03-25] M. Miura-Mattausch, S. Matsumoto, K. Mizoguchi, D. Miyawaki, H. J. Mattausch, S. Itoh, and K. Morikawa, "Test Circuits for Extracting Sub-100nm MOSFET Technology Variations with the MOSFET model HiSIM (Invited)," Proc. IEEE 2004 Int. Conference on Microelectronic Test Structures, Vol.17, No. 9.1, pp. 267-272. March, 2004.
[03-26] K. Konno, O.Matsushima, D. Navarro, and M. Miura-Mattausch, "Limit of Validity of the Drift-Diffusion Approximation for Simulation of Photodiode Characteristics," Appl. Phys. Lett., Vol. 84, No. 8, pp. 1398-1400, 2004.
[03-27] S. Nishiyama and K. Higuchi, "Doninant noise source of low frequency noise in AlGaAs/InGaAs HEMTs," Jpn. J. Appl. Phys., Vol. 42, pp. 2296-2299, 2003.
[03-28] M. Wada, S. Nishiyama, T. Nakamoto, and K. Higuchi, "Low Frequency Noise Sources in AlGaAs/InGaAs HEMTs," Ext. Abst. Int. Conf. on Solid State Devices and Materials, pp. 532-533, Tokyo, Sept. 16-18, 2003.
1.3 High-k dielectrics
[03-29] M. Yamato, H. Yamada, and T. Kikkawa, "Influence of interface layers and bottom electrodes on (Ba,Sr)TiO3 thin film leakage current," Ext. Abst. Int. Conf. on Solid State Devices and Materials, pp. 484-485, Tokyo, Sept. 16-18, 2003.
[03-30] S. Miyazaki, M. Narasaki, A. Suyama, M. Yamaoka, and H. Murakami, "Electronic Structure and Energy Band Offsets for Ultrathin Silicon Nitride on Si(100)," Appl. Surf. Sci., Vol. 216, No. 1-4, pp. 252-257, 2003.
[03-31] M. Yamaoka, H. Murakami, and S. Miyazaki, "Diffusion and Incorporation of Zr into Thermally-Grown SiO2 on Si(100)," Appl. Surf. Sci., Vol. 216, No. 1-4, pp. 223-227, 2003.
[03-32] M. Yamaoka, M. Narasaki, H. Murakami, and S. Miyazaki, "Photoemission Study of Ultrathin Hafnium Oxide Films Evaporated on Si(100)," Semiconductor Technology: Proc. of 2002 Electrochemical Society Int. Semicond. Tech. Conf., pp. 229-236, 2003.
[03-33] S. Miyazaki, H. Yamashita, H. Nakagawa, and M. Yamaoka, "Photoemission Study of Interfacial Oxidation in ZrO2/Sub-Nanometer SiONx/Si(100) Stacked," Mat. Res. Soc. Symp. Proc. Vol. 747, pp. 281-286, 2003.
[03-34] M. Yamaoka, A. Ohta, and S. Miyazaki, "Characterization of Hafnium Diffusion into Thermally-Grown SiO2 on Si(100)," Ext. Abst. Int. Conf. on Solid State Devices and Materials, pp. 810-811, Tokyo, Sept. 16-18, 2003.
[03-35] A. Ohta, M. Yamaoka, and S. Miyazaki, "Photoelectron Spectroscopy of Ultrathin Yttrium Oxide Films on Si(100)," 13th Bi-annual Conf. on Insulating Films on Semiconductors, GS20, Barcelona, June18-20, 2003.
[03-36] H. Nakagawa, A. Ohta, F. Takeno, H. Murakami, and S. Miyazaki, "Characterization of Interfacial Oxide Layers in Heterostructures of Zirconium Oxides Formed on Si(100) and NH3-nitrided Si(100) surfaces," The 7th International Conference on Atomically Controlled Surfaces, Interfaces and Nanostructures, p. 253(20D72), Nara, November 16-20, 2003.
[03-37] A. Ohta, S. Miyazaki, H. Murakami, T. Kawahara, and K. Torii, "Characterization of Dielectric Stack Structures of Hafnium Aluminate and Silicon Dioxide formed on Si(100)," The 7th International Conference on Atomically Controlled Surfaces, Interfaces and Nanostructures, p. 255(20D74), Nara, November 16-20, 2003.
1.4 Interconnect technologies
[03-38] Y. Hara, S. Yokoyama, and K. Umeda, "Compact Branched Optical Waveguides Using High-Index-Contrast Stacked Structure," Optical Review Vol. 10, No. 5, pp. 357-360, 2003.
[03-39] Z. Wang, H. Sakaue, S. Shingubara, and T. Takahagi,
"Influence of surface oxide of sputtered TaN on displacement plating of Cu
[03-40] Z. Wang, O. Yaegashi, H. Sakaue, T. Takahagi, and S. Shingubara,
"Suppression of native oxide growth in sputtered TaN films and its
application to Cu electroless plating
[03-41] Z. Wang , O. Yaegashi, H. Sakaue, T. Takahagi, and S.Shingubara,
"Highly adhesive electroless Cu layer formation using an ultra thin ionized
cluster beam (ICB)-Pd catalytic layer for sub-100 nm Cu interconnections
[03-42] S. Shingubara,Z. Wang, O. Yaegashi, R. Obata, H. Sakaue, and T. Takahagi, "Bottom-up Fill of Copper in High Aspect Ratio Via Holes by Electroless Plating," Technical Digest of IEEE IEDM, S 6.3, 2003.
1.5 Low-k interlayer dielectrics
[03-43] S. Kuroki, T. Kikkawa, H. Kochiya, and S. Shishiguchi, "Direct Patterning of Low-k Dielectric Films using X-Ray Lithography," Jpn. J. Appl. Phys., Vol. 42, No. 4B, pp. 1907-1910, 2003.
[03-44] N. Mikami, N. Hata, T. Kikkawa, and H. Machida, "Robust self-assembled monolayer as diffusion barrier for copper metallization," Appl. Phys. Lett., Vol. 83, No. 25, pp. 5181-5183, 2003.
[03-45] Xia Xiao, N. Hata, K. Yamada, and T. Kikkawa, " Mechanical properties of periodic porous silica low-k films determined by the twin transducer surface acoustic wave technique," Review of Scientific Instruments, Vol. 74, No. 10, pp. 4539-4541, 2003.
[03-46] K. Yamada, Y. Oku, N. Hata, S. Takada, and T. Kikkawa, "Effects of surfactants on the properties of ordered periodic porous silica films," Jpn. J. Appl. Phys., Vol. 42, No. 4B, pp. 1840-1842, 2003.
[03-47] S. Kuroki, T. Hirota, and T. Kikkawa, "A Novel Photosensitive Porous Low-k Interlayer Dielectric Film," Ext. Abst. Int. Conf. on Solid State Devices and Materials, pp. 468-469, Tokyo, Sept. 16-18, 2003.
[03-48] S. Sakamoto, S. Kuroki, and T. Kikkawa, "Influence of Humidity on Electrical Characteristics of Porous Silica Films," Ext. Abst. Int. Conf. on Solid State Devices and Materials, pp. 478-479, Tokyo, Sept. 16-18, 2003.
[03-49] S. Fujisawa, T. Kikkawa and T. Kizuka, "Direct Observation of Electromigration and Induced Stress in Cu Nanowire," Jpn. J. Appl. Phys., Vol. 42, pp. L1433-L1435, 2003.
[03-50] N. Hata, C. Negoro, S. Takada, X. Xiao, K. Yamada, and T. Kikkawa, "Integrated Characterization of Porous Low-k Films for Identifying Killer Pores and Micropores," Proceedings of IEEE International Interconnect Technology Conference, pp. 51-53, San Francisco, June 2-4, 2003.
[03-51] H. Miyoshi, H. Matsuo, Y. Oku, H. Tanaka, K. Yamada, N. Mikami, S. Takada, N. Hata, and T. Kikkawa, "Theoretical analysis of ultra low-k porous films with periodic pore arrangement and high elastic modulus," Proceedings of IEEE International Interconnect Technology Conference, pp. 57-59, San Francisco, June 2-4, 2003.
[03-52] N. Mikami, N .Hata, T. Yoshino, T,Kikkawa, and H. Machida, "A new self-assembled monolayer as a robust diffusion for Cu interconnect," Advanced Metallization Conference, pp. 68-69, 2003.
[03-53] C. Negoro, N. Hata , K. Yamada, and T. Kikkawa, "Non-destructive characterization of a series of periodic porous silica films by in-situ spectroscopic ellipsometry in a vapor cell," Advanced Metallization Conference, pp. 92-93, 2003.
[03-54] Y. Takenobu, N. Hata, and T. Kikkawa, "Evalution of Copper Ion Drift in Low-Dielectric Constant Interlayer Films by Transient Capacitance Spectroscopy," Materials Research Society, Symposium Proceedings, Vol. 766, pp. 217-222, 2003.
[03-55] N. Hata, C. Negoro, S. Takada, K. Yamada, Y. Oku, and T. Kikkawa, "Advanced characterization of ultra- low-k periodic porous silica films-pore size distribution, pore-diameter anisotropy, and size and macroscopic isotropy of domain structure," Materials Research Society, Symposium Proceedings, Vol. 766, pp. 191-195, 2003.
[03-56] C. Negoro, N. Hata, and T. Kikkawa, " Nondestructive Characterization of Pore Size Distributions in Porous Low-K Films by in-situ Spectroscopic Ellipsometry in Vapor Cell," Ext. Abst. Int. Conf. on Solid State Devices and Materials, pp. 78-79, Tokyo, Sept. 16-18, 2003.
[03-57] Y. Seino, R. Ichikawa, H. Tanaka, and T. Kikkawa, "Accurate measurement of mechanical properties of nanoporous silica ultra-low-k films," Ext. Abst. Int. Conf. on Solid State Devices and Materials, pp. 80-81, Tokyo, Sept. 16-18, 2003.
[03-58] S. Takada, N. Hata, Y. Seino, K. Yamada, Y. Oku, and T. Kikkawa, "Mechanical Property and Skeletal Silicate Structure of Periodic Porous Silica Films," Ext. Abst. Int. Conf. on Solid State Devices and Materials, pp. 82-83, Tokyo, Sept. 16-18, 2003.
[03-59] X. Xiao, N. Hata, K. Yamada, H. Tanaka, and T. Kikkawa, "Determination of the Mechanical Properties of Thin Periodic Porous Silica Films by Laser-Generated Surface Acoustic Wave Technique," Ext. Abst. Int. Conf. on Solid State Devices and Materials, pp. 84-85, Tokyo, Sept. 16-18, 2003.
[03-60] H. Matsuo, A. Ishikawa, and T. Kikkawa, "In-situ Measurement of Friction Force during Cu Chemical Mechanical Polishing," Ext. Abst. Int. Conf. on Solid State Devices and Materials, pp. 254-255, Tokyo, Sept. 16-18, 2003.
[03-61] N. Hata, C. Negoro, K. Yamada, and T. Kikkawa, "Control of Pore Size and Porosity in Periodic Porous Silica Low-k Films," Ext. Abst. Int. Conf. on Solid State Devices and Materials, pp. 258-259, Tokyo, Sept. 16-18, 2003.
[03-62] Y. Oku, K. Yamada, T. Goto, Y. Seino, A. Ishikawa, T. Ogata, K. Koumura, N. Fujii, N. Hata, R. Ichikawa, T. Yoshino, C. Negoro, A. Nakano, Y. Sonoda, S. Takeda, H. Miyoshi, S. Oike, H. Tanaka, H. Matsuo, K. Kinoshita, and T. Kikkawa, "Novel Self-Assembled Ultra-Low-K Porous Silica Films with High Mechanical Strength for 45nm BEOL Technology," IEEE International Electron Devices Meeting Technical Digest, pp. 139-142, 2003.
[03-63] J. Kawahara, A. Nakano, N. Kunimi, K. Kinoshita, Y. Hayashi, A. Ishikawa, Y. Seino, T. Ogata, H. Takahashi, Y. Sonoda, T. Yoshino, T. Goto, S. Takeda, R. Ichikawa, H. Miyoshi, H. Matsuo, S. Adachi, and T. Kikkawa, "A New Plasma-Enhanced Co-Polymerization (PCP)Technology for Reinforcing Mechanical Properties of Organic Silica Low-K/Cu Interconnects on 300mm Wafers," IEEE International Electron Devices Meeting Technical Digest, pp. 143-146, 2003.
1.6 Wireless interconnect technologies
[03-64] A.B.M. H. Rashid, S. Watanabe, and T. Kikkawa, "Characteristics of Integrated Antenna on Si for On-Chip Wireless Interconnect," Jpn. J. Appl. Phys., Vol. 42, No. 4B, pp. 2204-2209, 2003.
[03-65] T. Kikkawa, A.B.M. H. Rashid, and S.Watanabe, "Effect of silicon substrate on the transmission characteristics of integrated antenna," Proc. 2003 IEEE Topical Conference on Wireless Communication Technology, S06P09, Honolulu, Oct. 15-17, 2003.
[03-66] A.B.M. H. Rashid, S. Watanabe, and T. Kikkawa, "Crosstalk Isolation of Monopole Integrated Antenna on Si for ULSI Wireless Interconnect," Proceedings of IEEE International Interconnect Technology Conference, pp. 156-158, San Francisco, June 2-4, 2003.
[03-67] A.B.M. H. Rashid, S.Watanabe and T. Kikkawa, "Inter-chip Wireless Interconnection using Si Integrated Antenna," Ext. Abst. Int. Conf. on Solid State Devices and Materials, pp. 394-395, Tokyo, Sept. 16-18, 2003.
[03-68] S. Watanabe, A.B.M. H. Rashid, and T. Kikkawa, "Effect of High Resistivity Si Substrate on Antenna Transmission Gain for On-Chip Wireless Interconnects," Ext. Abst. Int. Conf. on Solid State Devices and Materials, pp. 668-669, Tokyo, Sept. 16-18, 2003.
1.7 CVD and contamination/particle control
[03-69] M. Kohno, T. Kitajima, S. Hirae, and S. Yokoyama, "Evaluation of Surface Contamination by Noncontact Capacitance Method under UV Irradiation," Jpn. J. Appl. Phys., Vol. 42, No. 9A, pp. 5837-5843, 2003.
[03-70] M. Kohno, T. Kitajima, S. Hirae, and S. Yokoyama, "Investigation of Surface Contamination on Silicon Oxide after HF Etching by Noncontact Capacitance Method," Jpn. J. Appl. Phys., Vol. 42, Part 1, No. 12, pp. 7601-7602, 2003.
[03-71] Q.D.M. Khosru, S. Yokoyama, A. Nakajima, K. Shibahara, T. Kikkawa, H. Sunami, and T. Yoshino, "Organic Contamination Dependence of Process Induced Interface Trap Generation in Ultrathin Oxide Metal Oxide Semiconductor Transistors," Jpn. J. Appl. Phys., Vol. 42, Part 2, No. 12A, pp. L1429-L1432, 2003.
[03-72] H. Habuka, Y. Shimazaki, S. Okamura, F. Sugimoto, T. Takeuchi, M. Aihara, M. Shimada, and K. Okuyama, "Time-dependent Airborne Organic Contamination on Silicon Wafer Surface Stored in a Plastic Box," Jpn. J. Appl. Phys., Part 1, Vol. 42, No. 4A, pp. 1575-1580, 2003.
[03-73] M. Adachi, S. Tsukui, and K. Okuyama, "Nanoparticle Formatioin Mechanism in CVD Reactor with Ionization of Source Vapor," J. Nanoparticle. Res., Vol. 5, No.1, pp. 31-38, 2003.
[03-74] K. Nakaso, B. Han, K.H. Ahn, M. Choi, and K. Okuyama, "Synthesis of Non-agglomerated Nanoparticles by An Electroscpray Assisted Chemical Vapor Deposition (ES-CVD) Method," J. Aerosol. Sci., Vol. 34, pp. 869-881, 2003.
[03-75] H. Setyawan, M. Shimada, Y. Imajo, Y. Hayashi, and K. Okuyama, "Characterization of Particle Contamination in Process Steps During Plasma Enhanced Chemical Vapor Deposition Operation," J. Aerosol. Sci., Vol. 34, No. 7, pp. 923-936, 2003.
[03-76] Nakaso, K. Okuyama, M. Shimada, and S.E. Pratsinis, "Effect of Reaction Tempearture on VD-made TiO2 Primary Particle Diameter," Chem. Eng. Sci., Vol. 58, No. 15, pp. 3327-3335, 2003.
[03-77] H. Setyawan, M. Shimada, Y. Hayashi, K. Okuyama, and S. Yokoyama, "Particle Formation and Trapping Behavior in a TEOS/O2 Plasma and Their Efects on Contamination of a Si Wafer," Aerosol. Sci. Tech., Vol. 38, No. 2, pp. 120-127, 2004.
[03-78] 近藤郁, 今城祐二, 島田学, 奥山喜久夫, "プラズマプロセス中でのダスト粒子の捕捉挙動の吸引法による計測," 化学工学論文集, Vol. 29, No. 4, pp. 513-520, 2003.
[03-79] 島田学, "プラズマCVDチャンバー内におけるパーティクル挙動の可視化-ガス中パーティクルと基板 コンタミネーションとの関係の検討-," クリーンテクノロジー, Vol. 13, No. 6, pp. 11-15, 2003.
[03-80] 守屋剛, 島田学, 奥山喜久夫, "プラズマを用いた半導体製造装置内のパーティクル発生・成長・挙動の可視化," 空気清浄, Vol. 4, No. 3, pp. 36-45, 2003.
[03-81] Y. Itoh, I.W. Lenggoro, K. Okuyama, L. Madler, and S.E. Pratsinis, "Size Tunable Synthesis of Highly Crystalline BaTiO3 nanoparticles using Salt-Assisted Spray Pyrolysis," J. Nanoparticle Res., Vol. 5, No. 3-4, pp. 191-198, 2003.
[03-82] F. Iskandar, L. Gradon, and K. Okuyama, "Control of the Morphology of Nanostructured Particles Prepared by the Spray Drying of a Nano-particle Sol," J. Coll. Interface Sci., Vol. 265, No. 2, pp. 296-303, 2003.
[03-83] Mikrajuddin, T. Morimoto, and K. Okuyama, "Generating blue and red luminescence from ZnO/polyethylene glycol nanocomposites prepared by in-situ method," Adv. Funct. Mater., Vol. 13, No. 10, pp. 800-804, 2003.
[03-84] B. Han, M. Shimada, K. Okuyama, and M. Choi, "Classification of Monodisperse Aerosol Particles Using an Adjustable Soft X-ray Charger," Powder Technol., Vol. 135-136, No. 2, pp. 336-344, 2003.
1.8 Atomic scale processes
[03-85] A. Nakajima, Q.D.M. Khosru, T. Kasai, and S. Yokoyama, "Carrier Mobility in p-MOSFET with Atomic-Layer-Deposited Si-Nitride/SiO2 Stack Gate Dielectrics," IEEE Electron Device Lett., Vol. 24, pp. 472-474, 2003.
[03-86] A. Nakajima, Q. D.M. Khosru, T. Yoshimoto, T. Kasai, and S. Yokoyama, "High quality atomic-layer deposited ultrathin Si-nitride gate dielectrics with low density of interface and bulk traps," Appl. Phys. Lett., Vol. 84, No. 2, pp. 335-337, 2003.
[03-87] H. Ishii, A. Nakajima, and S. Yokoyama, "Growth and electrical properties of atomic-layer deposited ZrO2/Si-nitride stack gate dielectrics," J. Appl. Phys., Vol. 95, No. 2, pp. 536-542, 2004.
[03-88] A. Nakajima, H. Ishii, T. Kitade, and S. Yokoyama, "Atomic-Layer-Deposited Ultrathin Si-Nitride Gate Dielectrics ---A Better Choice for Sub-tunneling Gate Dielectrics---," Technical Digest of the 2003 IEEE International Electron Devices Meeting, pp. 657-660, Washington, D.C., Dec. 8-10, 2003.
2 Self-assembling techniques and quantum structures
2.1 Silicon quantum dots and quantum electronics
[03-89] T. Kitade, K. Ohkura, and A. Nakajima, "Periodic Coulomb oscillation in highly doped Si single-electron transistor," Ext. Abst. Int. Conf. on Solid State Devices and Materials, pp. 584-585, Tokyo, September 16-18, 2003.
[03-90] T. Kitade and A. Nakajima, "Application of Highly-Doped Si Single-Electron Transistors to an Exclusive-NOR Operation," Jpn. J. Appl. Phys., Vol. 43, No. 3B, pp. L418-L420, 2004.
[03-91] A. Nakajima, "Silicon Quantum Dots," Encyclopedia of Nanoscience and Nanotechnology, H. S. Nalwa (ED.), American Scientific Publishers, U. S. A., Vol. 9, pp. 837-857, 2004.
[03-92] M. Ikeda, Y. Shimizu, H. Murakami and S. Miyazaki, "Multiple-Step Electron Charging in Silicon-Quantum-Dot Floating Gate Metal-Oxide-Semiconductor Memories," Jpn. J. Appl. Phys., Vol. 42, No. 6B, pp. 4134-4137, 2003.
[03-93] Y. Darma, R. Takaoka, H. Murakami, and S. Miyazaki, "Self-assembling formation of silicon quantum dots with a germanium core by low-pressure chemical vapor deposition," Nanotechnology, Vol. 14, pp. 413-415, 2003.
[03-94] Y. Darma, H. Murakami, and S. Miyazaki, "Formation of Nanometer Silicon Dots with Germanium Core by Highly-Selective Low-Pressure Chemical Vapor Deposition," Jpn. J. Appl. Phys., Vol. 42, No. 6B, pp. 4129-4133, 2003.
[03-95] K. Takeuchi, H. Murakami, and S. Miyazaki, "Electronic Charging State of Si Quantum Dots formed on Ultrathin SiO2 as Evaluated by AFM/Kelvin Probe Method," Proc. of 2002 Electrochemical Society Internat. Semicond. Tech. Conf, pp. 1-8, 2003.
[03-96] M. Ikeda, Y. Shimizu, T. Shibaguchi, H. Murakami, and S. Miyazaki, "Multiple-Step Electron Charging in Si Quantum-Dot Floating Gate nMOSFETs," Ext. Abst. Int. Conf. on Solid State Devices and Materials, pp. 846-847, Tokyo, Sept. 16-18, 2003.
[03-97] Y. Darma, K. Takeuchi, and S. Miyazaki, " Electronic Charged States of Single Si Quantum Dots with Ge Core as Detected by AFM/Kelvin Probe Technique," Ext. Abst. Int. Conf. on Solid State Devices and Materials, pp. 300-301, Tokyo, Sept. 16-18, 2003.
[03-98] Y. Darma and S. Miyazaki, "Characterization of Electronic Transport Through Si Dot with Ge Core Using AFM Conducting Probe," International Microprocesses and Nanotechnology Conference, pp. 22-23, Tokyo, October 29-31, 2003.
[03-99] Y. Darma and S. Miyazaki, "Thermal Stability of Nanometer Dot Consisting of Si Clad and Ge Core as Detected by Raman and Photoemission Spectroscopy," 2003 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices, pp. 145-149 (7.3), Busan, June 30-July 2, 2003.
[03-100] T. Shibaguchi, Y. Shimizu, M. Ikeda, H. Murakami, and S. Miyazaki, "Analysis of Charging Characteristics in MOSFETs with a Si-Quantum-Dots Floating Gate," 2003 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices, pp. 151-154 (7.4), Busan, June 30-July 2, 2003.
[03-101] Y. Darma, H. Murakami, and S. Miyazaki, "Influence of Thermal Annealing on Compositional Mixing and Crystallinity of Highly Selective Grown Si Dots with Ge Core," 1st Intern. SiGe Technology and Device Meeting, pp. 209-210(P2-45), Nagoya, Jan. 15-17, 2003.
[03-102] R. Masuyama, A. Higashi, K. Tanaka, Y. Kadoya, and M. Yamanishi, "Broadband photon-number squeezing in light-emitting diodes at low photon-flux levels," Appl. Phys. Lett., Vol. 83, p. 1113, 2003.
2.2 Nanoscale structures
[03-103] S. Shingubara,
"Fabrication of nanomaterials using porous alumina templates
[03-104] S. Shingubara, Y. Murakami, K. Morimoto, H. Sakaue, and T. Takahagi,
"Formation of aluminum nanodot array by combination of nanoindentation and anodic
oxidation of aluminum
3 Technologies for intelligent systems
[03-105] T. Koide, Y. Yano, and H. J. Mattausch, "An Associative Memory for Real-Time Applications Requiring Fully-Parallel Nearest Manhattan-Distance Search," 11th Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI’2003), pp. 200-205, April, 2003.
[03-106] S. Fukae, N. Omori, T. Koide, H.J. Mattausch, T. Inoue, and T. Hironaka, "Optimized Bank-Based Multi-Port Memories through a Hierarchical Multi-Bank Structure," 11th Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI’2003), pp. 323-330, April, 2003.
[03-107] Z. Zhu, K. Johguchi, H.J. Mattausch, T. Koide, T. Hirakawa, and T. Hironaka, "High Access Bandwidth Multi-Port-Cache Design with Compact Hierarchical 1-Port-Bank Structure," 11th Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI’2003), pp. 394-400, April, 2003.
[03-108] Z. Zhu, K. Johguchi, H.J. Mattausch, T. Koide, T. Hirakawa, and T. Hironaka, "High-Speed and Low-Power Multi-Port-Cache," Proceedings of COOL Chips VI, p. 76, 2003.
[03-109] H. Noda, K. Inoue, H.J. Mattausch, T. Koide and K. Arimoto, "A Cost-Efficient Dynamic Ternary CAM in 130 nm CMOS Technology with Planar Complementary Capacitors and TSR Architecture," 2003 Symposium on VLSI Circuits, Digest of Technical Papers, pp. 83-84, 2003.
[03-110] Y. Harada, T. Morimoto, T. Koide, and H.J. Mattausch, "CMOS Test Chip for a High-Speed Digital Image-Segmentation Architecture with Pixel-Parallel Processing," Proceedings of the 2003 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC’2003), pp. 284-287, 2003.
[03-111] Z. Zhu, K. Johguchi, H.J. Mattausch, T. Koide, T. Hirakawa, and T. Hironaka, "A Novel Hierarchical Multi-Port Cache," Proceedings of the 29th European Solid-State Circuits Conference (ESSCIRC’2003), pp. 405-408, Estoril, Portugal, September 16-18, 2003.
[03-112] T. Morimoto, Y. Harada, T. Koide, and H.J. Mattausch, "Low-Power Real-Time Region-Growing Image-Segmentation in 0.35 μm CMOS due to Subdivided-Image and Boundary-Active-Only Architectures," Ext. Abst. Int. Conf. on Solid State Devices and Materials, pp. 146-147, Tokyo, Sept. 16-18, 2003.
[03-113] T. Sueyoshi, H. Uchida, Y. Mitani, K. Hiramatsu, H.J. Mattausch, T. Koide, and T. Hironaka, "Bank-Type Multiport Register File for Highly-Parallel Processors," Ext. Abst. Int. Conf. on Solid State Devices and Materials, pp. 400-401, Tokyo, Sept. 16-18, 2003.
[03-114] K. Johguchi, Z. Zhu, T. Hirakawa, T. Koide, T. Hironaka, and H.J. Mattausch, "Combined Data/Instruction Cache with Bank-Based Multi-Port Architecture," Ext. Abst. Int. Conf. on Solid State Devices and Materials, pp. 152-153, Tokyo, Sept. 16-18, 2003.
[03-115] S. Fukae, N. Omori, T. Koide, H.J. Mattausch, and T. Hironaka, "A Hierarchical 512-Kbit SRAM with 8 Read/Write Ports in 130 nm CMOS," Ext. Abst. Int. Conf. on Solid State Devices and Materials, pp. 150-151, Tokyo, Sept. 16-18, 2003.
[03-116] T. Morimoto, Y. Harada T. Koide, and H.J. Mattausch, "350 nm CMOS Test-Chip for Architecture Verification of Real-Time QVGA Color-Video Segmentation at the 90 nm Technology Node," Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC’2004), pp. 531-532, 2004.
[03-117] T. Sueyoshi, H. Uchida, Y. Mitani, K. Hiramatsu, H.J. Mattausch, T. Koide, and T. Hironaka, "Compact 12-Port Multi-Bank Register File Test Chip in 0.35 μm CMOS for Highly Parallel Processors," Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC’2004), pp. 551-552, 2004.
[03-118] Y. Yano, T. Koide, and H.J. Mattausch, "Associative Memory with Fully Parallel Nearest-Manhattan-Distance Search for Low-Power Real-Time Single-Chip Applications," Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC‘2004), pp. 543-544, 2004.
[03-119] H. Noda, K. Inoue, M. Kuroiwa, A. Amo, A. Hachisuka, H.J. Mattausch, T. Koide, S. Soeda, K. Dosaka, and K. Arimoto, "A 143MHz, 1.1W, 4.5Mb dynamic TCAM with hierarchical searching and shift redundancy architecture," IEEE International Solid-State Circuits Conference Digest of Tech. Papers (ISSCC’2004), pp. 208-209, 2004.
[03-120] T. Sasaki, T. Inoue, N, Omori, T. Hironaka, H.J. Mattausch, and T. Koide, "Chip Size and Performance Evaluations of Shared Cache for On-chip Multiprocessors," IEICE Trans. on Information & Systems Part 1, Vol. J87-D-I, pp. 350-363, 2004 (in Japanese).
[03-121] T. Morimoto, Y. Harada, T. Koide, and H.J. Mattausch, "Efficient Video-Picture Segmentation Algorithm for Cell-Network-Based Digital CMOS Implementation," IEICE Trans. on Information & Systems, Vol. E87-D, pp. 500-503, 2004.
[03-122] S. Fukae, T. Inoue, H.J. Mattausch, T. Koide, and T. Hironaka, "Distributed against centralized crossbar function for realizing bank-based multiport memories," IEE Electronics Letters, Vol. 40, pp. 101-103, 2004.
[03-123] K. Johguchi, Z. Zhu, T. Hirakawa, T. Koide, T. Hironaka, and H.J. Mattausch, "Distributed-crossbar architecture for area-efficient combined data/instruction caches with multiple ports," IEE Electronics Letters Vol. 40, pp. 160-162, 2004.
[03-124] A. Iwata, "Advanced Design for Analog-RF and Digital Mixed LSIs- Crosstalknoise Evaluaiton and Reduction (Invited)," Proc. of the 11th Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI’2003), pp. 17-22, Hiroshima, April 3, 2003.
[03-125] T. Yoshida, T. Mashimo, M. Akagi, A. Iwata, M. Yoshida, and K. Uematsu, "A Design of Neural Signal Sensing LSI with Multi-Input-Channels," Proc. of the 11th Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI’2003), pp. 206-210, Hiroshima, April 3, 2003.
[03-126] S. Kameda and T. Yagi, " A silicon retina system that calculates direction of motion," Proc. The 2003 IEEE International Symposium on Circuits and Systems, Vol. IV, pp. 792-795, Bangkok, Thailand, May, 2003.
[03-127] K. Katayama and A. Iwata, "A Pulse-Coupled Neural Network Simulator Using a Programmable Gate Array Technique," IEICE Trans. Inf.& Syst., Vol. E86-D, No. 5, pp. 872-881, May, 2003.
[03-128] T Morie, T. Matsuura, and A. Iwata, "Pulse Modulation VLSI Implementation of Clustering Algorithm Based on Stochastic Association Model, Artificial Neural Networks and Neural Information Processing," ICANN/ICONIP 2003 International Conference, pp. 434-437, Istanbul, June 26-29, 2003.
[03-129] T. Nakano, H. Ando, H. Ishizu, T. Morie, and A. Iwata, "Coarse Image Region Segmentation Using Resistive-fuse Networks Implemented in FPGA," The 7th World Multiconference on Systemics, Cybernetics and Informatics (SCI 2003), Proceedings, Vol. IV, pp. 186-191, Orlando, July 27-30, 2003.
[03-130] S. Kameda and T. Yagi, "An analog silicon retina with multi-chip configuration," International Joint Conference on Neural Networks 2003 Conference Proceedings, pp. 387-392, Oregon, 2003.
[03-131] T. Nakano, T. Morie, and A. Iwata, "A Face/Object Recognition System Using FPGA Implementation of Coarse Region Segmentation," SICE Annual Conference 2003, Organized session: Intelligent Integrated Systems and its Applications - Embedding Intelligence into Integrated Circuits, pp. 1418-1423, Fukui, Aug. 4-6, 2003.
[03-132] K. Korekado, T. Morie, O. Nomura, H. Ando, T. Nakano, M. Matsugu, and A. Iwata, "A Convolutional Neural Network VLSI for Image Recognition Using Merged/Mixed Analog-Digital Architecture," 7th Int. Conf. on Knowledge-Based Intelligent Information and Engineering Systems (KES'2003), pp. II-169-176, Oxford, Sept. 3-5, 2003.
[03-133] T. Morie, T. Matsuura, M. Nagata, and A. Iwata, "A Multi-Nano dot Floating-Gate MOSFET Circuit for Spiking Neuron Models," IEEE Trans. Nanotechnology, Vol. 2, No. 3, pp. 158-164, Sept., 2003.
[03-134] W. K. Chu, N. Verghese, H-J. Cho, K. Shimazaki, H. Tsujikawa, S. Hirano, S. Doushoh, M. Nagata, A. Iwata, and T. Ohmoto, "A Substrate Noise Analysis Methodology for Large-Scale Mixed-Signal ICs," Proceedings of IEEE 2003 Custom Integrated Circuits Conference (CICC 2003), pp. 369-372, Sept., 2003.
[03-135] S. Kameda and T. Yagi, "An analog VLSI Chip Emulating Sustained and Transient Response Channels of the Vertebrate Retina," EEE Transactions on Neural Networks, Vol. 14, No. 5, pp. 1405-1412, Sept., 2003.
[03-136] T. Yoshida, T. Mashimo, M. Akagi, A. Iwata, M. Yoshida, and K. Uematsu, "A Design of Neural Signal Sensing LSI with Multi-Input Channels," IEICE Trans. Fundamentals, Vol. E87-A, pp. 376-383, Feb., 2004.
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