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2002 (2002 April - 2003 March)

  1. Advanced device process and material technologies for ULSI
  2. Self assembling technique and quantum structure
  3. Technologies for intelligent systems

1. Advanced device, process, and material technologies for ULSI

1.1 Fabrication techniques for scaled MOS devices

[02-1] T. Amada, N. Maeda, and K. Shibahara, "Degradation in a Molybdenum-Gate MOS Structure Caused by N+ Ion Implantation for Work Function Control," Mat. Res. Soc. Symp. Proc. Vol. 716, pp. 299-314, 2002.

[02-2] K. Shibahara, "Ultra-Shallow Junction Formation with Antimony Implantation (Invited)," IEICE Trans. Electron., Vol. E.85-C, pp. 1091-1097, 2002.

[02-3] D. Notsu, N. Ikechi, Y. Aoki, N. Kawakami, and K. Shibahara, "Fabrication of 100 nm Width Fine Active-Region Using LOCOS Isolation," IEICE Trans. Electron., Vol. E85-C, pp. 1119-1123, 2002.

[02-4] K. Shibahara, D. Onimatsu, Y. Ishikawa, T. Oda, and T. Kikkawa, "Copper drift in low dielectric constanti Insulator films caused by O2 + primary ion beam," Appl. Surf. Sci., Vol. 203-204, pp. 387-390, 2002.

[02-5] A. Matsuno, K. Kagawa and Y. Niwatsukino, T. Nire, and K. Shibahara, "PULSE DURATION EFFECTS ON LASER ANNEAL SHALLOW JUNCTION," Proc. the 2nd Int. Semiconductor Tech. Conf. (ISTC), Vol. 2002-17, pp. 148-156, 2002.

[02-6] N. Maeda, D. Onimatsu, Y. Ishikawa and K. Shibahara, "Gate-Extension Overlap Control by Sb Tilt Implantation," Proc. the 2nd Int. Semiconductor Tech. Conf. (ISTC), Vol. 2002-17, pp. 165-171, 2002.

[02-7] 芝原 健太郎 (監訳), "タウア・ニン最新VLSIの基礎," 丸善, 2002.

[02-8] K. Kagawa, Y. Niwatsukino, M. Matsuno, and K. Shibahara, "Influence of pulse duration on KrF excimer laser annealing process for ultra shallow junction formation," Int. Workshop on Junction Tech. (IWJT), pp. 31-34, 2002.

[02-9] K. Kurobe, Y. Ishikawa, K. Kagawa, Y. Niwatsukino, A. Matsuno, and K. Shibahara, "Formation of Low-resistive Ultra-shallow n+/p Junction by Heat-assisted Excimer Laser Annealing," Int. Workshop on Junction Tech. (IWJT), pp. 35-36, 2002.

[02-10] H. Sunami, T. Furukawa, and T. Masuda, "ORIENTATION-DEPENDENT ANISOTROPIC TMAH ETCHANT APPLIED TO 3-D SILICON NANOSTRUCTURE FORMATION," Proc. Pacific Rim Workshop on Transducers and Micro/nano Technologies, pp. 367-372, Xiamen, July 22-24, 2002.

[02-11] T. Furukawa, H. Yamashita, and H. Sunami, "Corrugated-Channel Transistor (CCT) for Area-Conscious Applications," Ext. Abst. of International Symp. on Solid State Devices and Materials, Abs. No. A-3-2, pp. 139-140, Nagoya, Sept. 17-19, 2002.

[02-12] A. Takase, T. Kidera, and H. Sunami, "Field-Shield Trench Isolation with Self-Aligned Field Oxide," Ext. Abst. of International Symp. on Solid State Devices and Materials, Abs. No. A-7-4, pp. 694-695, Nagoya, Sept. 17-19, 2002.

1.2 Evaluation and modeling techniques for scaled MOS devices

[02-13] H. Kawano, M. Nishizawa, S. Matsumoto, S. Mitani, M. Tanaka, N. Nakayama, H. Ueno, M. Miura-Mattausch, and H. J. Mattausch, "A Practical Small-Signal Equivalent Circuit Model for RF-MOSFETs Valid Up to the Cut-Off Frequency," IEEE MTT-S Digest, pp. 2121-2124, Jun. 2002.

[02-14] 三浦 道子, 上野 弘明, "デバイスモデルと回路シミュレーション," 基礎講座,応用物理, 第71巻, 第6号, pp.726-730, 2002.

[02-15] M. Miura-Mattausch, D. Navarro, H. Ueno, S. Jinbou, H. J. Mattausch, K. Morikawa, S. Itoh, A. Kobayashi, and H. Masuda, "HiSIM : Accurate Charge Modeling Important for RF Era (invited)," Proc. Int. Conf. on Modeling and Simulation of Microsystems, pp. 258-261, Feb. 2003.

[02-16] Q. Ngo, D. Navarro, T. Mizoguchi, S. Hosokawa, H. Ueno, M. Miura-Mattausch, and C. Y. Yang, "Gate Current Partitioning in MOSFET Models for Circuit Simulation," Proc. Int. Conf. on Modeling and Simulation of Microsystems, pp.322-325, Feb. 2003.

[02-17] M. Miura-Mattausch, H. Ueno, H. J. Mattausch, S. Kumashiro, T. Yamaguchi, K. Yamashita, and N. Nakayama, "Circuit Simulation Models for Coming MOSFET Generations," IEICE Trans. Fundamentals, Vol. E85-A, pp. 740-748, 2002.

[02-18] K. Morikawa, H. Ueno, D. Kitamaru, M. Tanaka, T. Okagaki, M. Miura-Mattausch, H. J. Mattausch, S. Kumashiro, T. Yamaguchi, K. Yamashita, and N. Nakayama, "Quantum Effect in Sub-0.1 um MOSFET with Pocket Technologies and Its Relevance for the On-Current Condition," Jpn. J. Appl. Phys., Vol. 41, pp. 2359-2362, 2002.

[02-19] D. Navarro, K. Hisamitsu, T. Yamaoka, M. Tanaka, H. Kawano, H. Ueno, M. Miura-Mattausch, H. J. Mattausch, S. Kumashiro, T. Yamaguchi, K. Yamashita, and N. Nakayama, "Circuit-Simulation Model of Gate-Drain-Capacitance Changes in Small-Size MOSFETs Due to High Channel-Field Gradients," Proc. Int. Conf. on Simulation of Semiconductor Processes and Devices, pp. 51-54, Sep. 2002.

[02-20] H. Ueno, S. Jinbou, H. Kawano, K. Morikawa, N. Nakayama, M. Miura-Mattausch, and H. J. Mattausch, "Drift-Diffusion-Based Modeling of the Non-Quasistatic Small-Signal Response for RF-MOSFET Applications," Proc. Int. Conf. on Simulation of Semiconductor Processes and Devices, pp. 71-74, Sep. 2002.

[02-21] S. Jinbou, H. Ueno, H. Kawano, K. Morikawa, N. Nakayama, M. Miura-Mattausch, and H. J. Mattausch, "Analysis of Non-Quasistatic Contribution to Small-Signal Response for DeepSub-um MOSFET Technologies," Ext. Abst. Int. Conf. on Solid State Devices and Materials, pp. 26-27, Sep. 2002.

[02-22] N. Nakayama, H. Ueno, T. Inoue, T. Isa, M. Tanaka, and M. Miura-Mattausch, "A Self-Consistent Non-Quasi Static MOSFET Model for Circuit Simulation Based on Transient Carrier Response," Ext. Abst. Int. Conf. on Solid State Devices and Materials, pp. 408-409, Sep. 2002.

[02-23] H. Ueno, D. Kitamaru, K. Morikawa, M. Tanaka, M. Miura-Mattausch, H. J. Mattausch, S. Kumashiro, T. Yamaguchi, K. Yamashita, and N. Nakayama, "Impurity-Profile-Based Threshold-Voltage Model of Pocket-Implanted MOSFETs for Circuit Simulation," IEEE Trans. Electron Devices, Vol. 49, No. 10, pp. 1783-1789, Oct. 2002.

[02-24] K. Hisamitsu, H. Ueno, M. Tanaka, D. Kitamaru, M. Miura-Mattausch, H. J. Mattausch, S. Kumashiro, T. Yamaguchi, K. Yamashita, and N. Nakayama, "Temperature-Independence- Point Properties for 0.1um-Scale Pocket-Implant Technologies and the Impact on Circuit Design," Proc. of Asia and South Pacific Design Automation Conf., pp. 179-183, Jan. 2003.

[02-25] D. Navarro, H. Kawano, K. Hisamitsu, T. Yamaoka, M. Tanaka, H. Ueno, M. Miura-Mattausch, H. J. Mattausch, S. Kumashiro, T. Yamaguchi, K. Yamashita, and N. Nakayama, "Circuit-Simulation Model of Cgd Changes in Small-Size MOSFETs Due to High Channel-Field Gradients (invited)," IEICE Trans. Electron., Vol. E86-C, No. 3, pp. 474-480, Mar. 2003.

[02-26] M. Tanaka, H. Ueno, O. Matsushima, and M. Miura-Mattausch, "High-Electric-Field Electron Transport at Silicon/Silicon-Dioxide Interface Inversion Layer," Jpn. J. Appl. Phys., Vol. 42, No. 3B, pp. L280-L282, Mar. 2003.

[02-27] S. Nishiyama, T. Iwaki and K. Higuchi, "Low Frequency Noise Sources in AlGaAs/InGaAs HEMTs," Ext. Abst. the Int. Conf. on Solid State Devices and Materials, pp. 504-505, 2002.

[02-28] S. Nishiyama and K. Higuchi, "Dominant Noise Source of Low Frequency Fluctuation in AlGaAs/InGaAs HEMTs," Jpn. J. Appl. Phys., Vol. 42, pp. 2296-2299, 2003.

[02-29] M. Wada, S. Nishiyama, T. Nakamoto, and K. Higuchi, "Low Frequency Noise Caused by Substrate Current in AlGaAs/InGaAs HEMTs," Ext. Abst. the Int. Conf. On Solid State Devices and Materials, pp. 532-533, 2003.

[02-30] M. Miura-Mattausch, H. Ueno, M. Tanaka, H. J. Mattausch, S. Kumashiro, T. Yamaguchi, K. Yamashita and N. Nakayama, "HiSIM: A MOSFET Model for Circuit Simulation Connecting Circuit Performance with Technology (invited)," IEEE International Electron Devices Meeting Tech. Dig., pp. 109-112, 2002.

[02-31] S. Jinbou, H. Ueno, H. Kawano, K. Morikawa, N. Nakayama, M. Miura-Mattausch and H.J. Mattausch, "Analysis of Non-Quasistatic Contribution to Small-Signal Response for Deep Sub-um MOSFET Technologies," Ext. Abst. the International Conference on Solid State Devices and Materials, pp. 26-27, 2002

[02-32] D. Navarro, K. Hisamitsu, T. Yamaoka, M. Tanaka, H. Kawano, H. Ueno, M. Miura-Mattausch, H. J. Mattausch, S. Kumashiro, T. Yamaguchi, K. Yamashita and N. Nakayama, "Circuit-Simulation Model of Gate-Drain-Capacitance Changes in Small-Size MOSFETs Due to High Channel-Field Gradients," Proc. the IEEE International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), pp. 51-54, 2002.

[02-33] S. Jinbou, H. Ueno, H. Kawano, K. Morikawa, N. Nakayama, M. Miura-Mattausch and H.J. Mattausch, "Drift-Diffusion-Based Modeling of the Non-Quasistatic Small-Signal Response for RF-MOSFET Applications," Proc. the IEEE International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), pp. 71-74, 2002.

[02-34] H. Kawano, M. Nishizawa, S. Matsumoto, S. Mitani, M. Tanaka, N. Nakayama, H. Ueno, M. Miura-Mattausch and H.J. Mattausch, "A Practical Small-Signal Equivalent Circuit Model for RF-MOSFETs Valid Up to the Cut-Off Frequency," Proc. the IEEE International Microwave Symposium (IMS), pp. 2121-2124, 2002.

[02-35] S. Matsumoto, K. Hisamitsu, M. Tanaka, H. Ueno, M. Miura-Mattausch, H.J. Mattausch, S. Kumashiro, T. Yamaguchi, K. Yamashita, and N. Nakayama, "Validity of mobility universality for scaled metal-oxide-semiconductor field-effect-transistors down to 100 nm gate length," J. Appl. Phys. Vol. 92, pp. 5228-5232, 2002.

[02-36] M. Miura-Mattausch, H. Ueno, H. J. Mattausch, S. Kumashiro, T. Yamaguchi, K. Yamashita and N. Nakayama, "HiSIM: Self-Consistent Surface-Potential MOS-Model Valid Down to Sub-100nm Technologies (invited)," Proc. the IEEE International Conference on Modeling and Simulation of Microsystems (MSM), pp. 678-681, 2002.

[02-37] H. J. Mattausch, M. Suetake, D. Kitamaru, M. Miura-Mattausch, S. Kumashiro, N. Shigyo, S. Odanaka and N. Nakayama, "Simple nondestructive extraction of the vertical channel-impurity profile of small-size metal-oxide-semiconductor-field-effect transistors," Appl. Phys. Lett., Vol. 80, pp. 2994-2996, 2002.

1.3 Gate oxides and reliability issues

[02-38] S. Miyazaki, S. Shingubara, H. Sakaue, and T. Takahagi, "Off-time Dependence of Electromigration, MTF in Pulsed DC Stressing Tests," Mat. Res. Soc. Conf. Proc. ULSI-XVIII, pp. 279-284, 2003.

[02-39] H. Murakami, T. Mihara, S. Miyazaki and M. Hirose "Carrier Depletion Effect in the n+ Poly-Si Gate Side-Wall/SiO2 Interfaces as Evaluated by Gate Tunnel Leakage Current," Jpn. J. Appl. Phys., Vol. 41, No. 5A, pp. L512-L514, 2002.

[02-40] W. Mizubayashi, Y. Yoshida, S. Miyazaki and M. Hirose, "Quantitative Analysis of Oxide Voltage and Field Dependence of Time-Dependent Dielectric Soft Breakdown and Hard Breakdown in Ultrathin Gate Oxides," Jpn. J. Appl. Phys., Vol. 41 No. 4B, pp. 2426-2430, 2002.

[02-41] S. Miyazaki, "Characterization of Ultrathin Gate Dielectrics on Silicon by Photoelectron Spectroscopy," Proc. 2001 MRS Workshop Series-Alternatives on to SiO2 as Gate Dielectric for Future Si-Based Microelectronics, pp. 8-1-8-7, 2002.

1.4 High-k dielectrics

[02-42] H. Yamada, N. Fujiwara, M. Yamato, S. Miyazaki, F. Nishiyama and T. Kikkawa, "Influence of Electrodes on the Leakage Current In (Ba,Sr)TiO3 Thin films," Abstract of ECS International Semiconductor Technology Conference, E, Abs. No.108, 2002.

[02-43] S. Miyazaki "Characterization of high-k gate dielectric/silicon interfaces," Appl. Surf. Sci., Vol. 190/1-4, pp. 66-74, 2002.

[02-44] S. Miyazaki, M. Narasaki, M. Ogasawara and M. Hirose, "Chemical and electronic structure of ultrathin zirconium oxide films on silicon as determined by photoelectron spectroscopy," Solid State Electronics, Vol. 16, pp. 1679-1685, 2002.

[02-45] A. Suyama, H. Yokoi, M. Narasaki, W. Mizubayashi, H. Murakami and S. Miyazaki, "Photoemission Study of Aluminum Oxynitride/Si(100) Heterostructures - Chemical Bonding Features and Energy Band Lineup -," Ext. Abst. Inter. Conf. on Solid State Devices and Materials, pp. 760-761(C-8-3), Nagoya, Sept. 17-19, 2002.

[02-46] H. Murakami, W. Mizubayashi, H. Yokoi, A. Suyama and S. Miyazaki, "Electrical Characterization of Aluminum-Oxynitride Stacked Gate Dielectrics Prepared by a Layer-by-Layer Process of Chemical Vapor Deposition and Rapid Thermal Nitridation," Ext. Abst. Internat. Conf. on Solid State Devices and Materials, pp. 712-713(B-7-1), Nagoya, Sept. 17-19, 2002.

[02-47] M. Yamaoka, H. Murakami and S. Miyazaki, "Diffusion and incorporation of Zr into thermally-grown SiO2 on Si (100)," Appl. Surf. Sci. Vol. 216, pp. 223-227, 2003; 4th Internat. Symp. on Control of Semiconductor Interfaces, A4-3, Karuizawa, Oct. 21-25, 2002.

[02-48] S. Miyazaki, M. Narasaki and H. Murakami, "Electronic structure and energy band offsets for ultrathin silicon nitride on Si (100)," Appl. Surf. Sci., Vol. 216, pp. 252-257, 2003; 4th Internat. Symp. on Control of Semiconductor Interfaces, A5-3, Karuizawa, Oct. 21-25, 2002.

[02-49] M. Yamaoka, M. Narasaki, H. Murakami and S. Miyazaki, "PHOTOEMISSION STUDY OF ULTRATHIN HAFNIUM OXIDE FILMS EVAPORATED ON Si (100)," Proc. Electrochemical Society Intern. Semicond. Technol. Conf., Abs. No. 33, pp. 229-237, Tokyo, Sept. 12-14, 2002.

[02-50] S. Miyazaki, H. Yamashita, H. Nakagawa and M. Yamaoka, "Photoemission study of interfacial oxidation in ZrO2/sub-nanometer SiONx/Si(100) stacked structures," Proc. Mat. Res. Soc. Symp., Vol. 747, pp. 281-286, 2003; MRA Fall Meeting, V3.7, Boston, Dec. 2-6, 2002.

1.5 Interconnect technologies

[02-51] T. Kikkawa, N. Fujiwara, H. Yamada, S. Miyazaki, F. N.ishiyama, and M. Hirose, "Energy band structure of Ru/(Ba,Sr)TiO3/Si capacitor deposited by inductively-coupled plasma-assisted radio-frequency-magnetron plasma sputtering," Appl. Phys. Lett., Vol. 81, No.15, pp. 2821-2823, 2002.

[02-52] Z. Wang, T. Ida, H. Sakaue, S. Shingubara and T. Takahagi, "Electroless Plating of Copper on Metal-Nitride Diffusion Barriers by Displacement Plating," Electrochem. Solid-State Letters, Vol. 6 , No. 3, pp. C38-C41, 2003.

[02-53] Z. Wang, T. Ida, H. Sawa, H. Sakaue, S. Shingubara and T. Takahagi, "Direct Electroless Copper Plating on Barrier Metals without Pd Catalyst," Proc. of Advanced Metallization Conference 2001, MRS Conf. Proc.ULSI-XVII, pp. 185-190, 2002.

[02-54] Z. Wang, A. Furuya, K. Yasuda, H. Ikeda, T. Baba, M. Hagiwara, S. Toki, S. Shingubara, H. Kubota, and T. Ohmi, "Adhesion improvement of electroless copper to a polyimide film substrate by combining surface microroughening and imide ring cleavage," J. Adhesion Technology, Vol. 16, pp. 1027-1040, 2002.

[02-55] S. Fujisawa, T. Kikkawa, and T. Kizuka, "A Novel TEM/AFM/STM Microscopy for Cu Nano-Wire Electromigration," Ext. Abst. Inter. Conf. on Solid State Devices and Materials, pp. 50-52, 2002.

1.6 Low-k interlayer dielectrics

[02-56] N. Hata, Y. Oku, K. Yamada, and T. Kikkawa, "A New Approach of Thin-Film X-ray Diffraction /Scattering Analysis for Ultra-Low-k Dielectrics with Periodic Pore Structures," Proc. Materials Research Society Spring Meeting, Vol. 716, pp. 581-586, April 2002.

[02-57] Y. Oku, N. Nishiyama, S. Tanaka, K. Ueyama, N. Hata, and T. Kikkawa, "Novel periodic nanoporous silicate glass with high structural stability as low-k thin film," Proc. Materials Research Society Spring Meeting,Vol.716, pp. 587-592, April 2002.

[02-58] K. Uera, J. Kawahara, H. Miyoshi, N. Hata, and T. Kikkawa, "Dielectric Constant and Young's Modulus of Organic Low-k Materials Calculated by Molecular Orbital Method," Abstract of Advanced Metallization for ULSI Application, pp. 20-21, 2002; Proc.ULSIXVIII, Materials Research Society, pp. 643-648, 2003.

[02-59] C. Negoro, N. Hata , K. Yamada, H. S. Zhou, and T. Kikkawa, "Characterization of Porous Low-k Dielectrics by Gas Adsorption Techniques," Abstract of Advanced Metallization for ULSI Application, pp. 34-35, 2002, Proc. ULSIXVIII, Materials Research Society, pp. 273-278, 2003.

[02-60] T. Yoshino, N. Hata, and T. Kikkawa, "Evalution of Copper Ion Drift in Low-Dielectric Constant Interlayer Films by Transient Capacitance Spectroscopy," Proc. Materials Research Society , Vol. 766, pp. 217-222, 2003.

[02-61] N. Sasaki, T. Oda, and T. Kikkawa, "Influence of Metal Electrodes on Leakage Current in MSQ Films with or without Pores," Proc. ULSIXVIII, Materials Research Society, pp. 265-268, 2003.

[02-62] N. Hata, C. Negoro, S. Takada, K. Yamada, Y. Oku, and T. Kikkawa, "Advanced characterization of ultra-low-k periodic porous silica films-pore size distribution, pore-diameter anisotropy, and size and macroscopic isotropy of domain structure," Proc. Materials Research Society, Vol. 766, pp. 191-195, 2003.

[02-63] N. Hata, C. Negoro, K. Yamada, H. S. Zhou, Y. Oku, and T. Kikkawa, "Analysis of Pore Structures in Ultra Low-k Dielectrics," Ext. Abst. Internat. Conf. on Solid State Devices and Materials, pp. 496-497, Nagoya, Sept. 17-19, 2002.

[02-64] K. Yamada, Y. Oku, N. Hata, S. Takada and T. Kikkawa, "Structure control of periodic porous silica film for low-k application," Ext. Abst. Inter. Conf. on Solid State Devices and Materials, pp. 40-41, Nagoya, Sept. 17-19, 2002.

[02-65] Y. Oku, K. Yamada, N. Nishiyama, S. Tanaka, K. Ueyama, N. Hata and T. Kikkawa, "Effect of TEOS treatment on the properties of periodic nanoporous silica low-k film," Ext. Abst. Inter. Conf. on Solid State Devices and Materials, pp. 42-43, Nagoya, Sept. 17-19, 2002.

[02-66] S. Kuroki, T. Kikkawa, H. Kochiya, and S. Shishiguchi, "Direct Patterning of Low-k Dielectric Films using X-Ray Lithography," Ext. Abst. Inter. Conf. on Solid State Devices and Materials, pp. 464-465, Nagoya, Sept. 17-19, 2002.

[02-67] S. Sakamoto, K. Komura, and T. Kikkawa, "Effect of hexamethyldisilazane on the electrical characteristics of a porous silica thin film," Abstract of Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices, pp. 125-129, 2002.

[02-68] T. Kikkawa, "Present status and future trend of low-k dielectrics/interconnect technologies for ULSI (Invited)," Proc. 7th International Syposium on Plasma-and Process-Induced Damage, (American Vacuum Society, IEEE, Maui, USA), pp.154-157, 2002.

1.7 Wireless interconnect technologies

[02-69] A. B. M. H. Rashid, S. Watanabe and T. Kikkawa, "High Transmission Gain Integrated Antenna on Extremely High Resistivity Si for ULSI Wireless Interconnect," IEEE Electron Device Letters, Vol. 23, No. 12, pp. 731-733, December 2002.

[02-70] S. Watanabe, A. B. M. H. Rashid and T. Kikkawa, "Influence of Si Substrate Ground on Antenna Transmission Gain for On-Chip Wireless Interconnects," Abst. Advanced Metallization for ULSI Application, pp. 94-95, 2002, Conference Proceedings, pp.543-548.

[02-71] A. B. M. H. Rashid, S. Watanabe and T. Kikkawa, "Wireless Interconnection on Si using Integrated Antenna," Ext. Abst. Inter. Conf. on Solid State Devices and Materials, pp. 648-649, September 2002.

[02-72] A. B. M. H. Rashid, S. Watanabe, T. Kikkawa, X. Guo, and K. O, "Interference Suppression of Wireless Interconnecton in Si Integrated Antenna," Proc. International Interconnect Technology Conference (IEEE, San Francisco, USA, June 3-5), pp. 173-175, 2002.

1.8 CVD and contamination/particle control

[02-73] 島田学, 奥山喜久夫, "水晶振動子を用いたガス状汚染物質の付着モニタ -クリーンルーム内のガス汚染のリアルタイムモニタリングへの適応-," クリーンテクノロジー, Vol. 12, (9), pp. 34-37, 2002.

[02-74] 島田学, 奥山喜久夫, 本田重夫, 羽深等, "ガス状有機汚染物質の壁面付着量の実時間計測と付着挙動の評価," 空気清浄, Vol. 4, No. 4, pp. 275-281, 2003.

 

[02-75] H. Shinagawa, H. Setyawan, T. Asai, Y. Sugiyama, K. Okuyama, "An experimental and theoretical investigation of rarefied gas flow through circular tube of finite length," Chemical Engineering Science, Vol. 57, No. 19, pp. 4027-4036, 2002.

[02-76] 近藤郁, 今城祐二, 島田学, 奥山喜久夫, "半導体材料ガス中に浮遊する微粒子の光散乱法による検出," 粉体工学会誌, Vol. 39, No.11, pp. 806-812, 2002.

[02-77] H. Setywan, M. Shimada, K. Okuyama, "Characterization of fine particle trapping in a plasma-enhanced chemical vapor deposition reactor," J. Appl. Phys., Vol. 92, No. 9, pp. 5525-5531, 2002.

[02-78] H. Setyawan, M. Shimada, K. Ohtsuka, K. Okuyama, "Visualization and numerical simulation of fine particle transport in a low pressure parallel plate chemical vapor deposition reactor," Chemical Engineering Science, Vol. 57, No. 3, pp. 497-506, 2002.

[02-79] M. Shimada, K. Okuyama, S. Honda, H. Habuka, "Real-time measurement and evaluation of wall deposition behavior of gaseous organic contaminants," J. Jpn. Air Cleaning Assoc., Vol. 40, No. 4, pp. 275-281, 2002.

[02-80] T. Yoshino, S. Yokoyama and T. Fujii, "Influence of Organic Contaminant on Trap Generation in Thin SiO2 of Metal-Oxide-Semiconductor Capacitors," Jpn. J. Appl. Phys., Vol. 41, No. 7A, pp. 4750-4753, 2002.

[02-81] 横山新, 吉野雄信, 芝原健太郎, 中島安理, 吉川公麿, 角南英夫, Q. D. M. Khosru, "ウェハ保管環境のMOSデバイス特性への影響," エアロゾル研究, 第17巻, 第2号, pp. 96-104, 2002.

[02-82] M. Kohno, T. Kitajima, S. Hirae and S. Yokoyama, "Evaluation of Surface Contamination by Noncontact Capacitance Method under UV Irradiation," Ext. Abst. of the Int. Conf. on Solid State Devices and Materials, pp. 724-725, 2002.

[02-83] 横山新, 藤井敏昭, "クリーンルーム設計と運転・維持管理、第11章クリーンルームの技術動向と今後の展望 第1節スーパークリーンルーム," (株)情報機構, 2002年10月初版, pp. 211-222.

1.9 Atomic scale processes

[02-84] Q. D. M. Khosru, A. Nakajima, T. Yoshimoto, and S. Yokoyama, "Low Thermal-Budget Ultrathin NH3-Annealed Atomic-Layer-Deposited Si-Nitride/SiO2 Stack Gate Dielectrics With Excellent Reliability," IEEE Electron Device Lett., Vol. 23, pp. 179-181, 2002.

[02-85] Q. D. M. Khosru, A. Nakajima, T. Yoshimoto, and S. Yokoyama, "Reliable extraction of the energy distribution of Si/SiO2 interface traps in ultrathin metal-oxide-semiconductor structures," Appl. Phys. Lett., Vol. 80, pp. 3952-3954, 2002.

[02-86] Q. D. M. Khosru, A. Nakajima, T. Yoshimoto, and S. Yokoyama, "High quality NH3-annealed atomic layer deposited Si-nitride/SiO2 stack gate dielectrics for sub-100nm technology generations," Solid State Electron., Vol. 46, pp. 1659-1664, 2002.

[02-87] A. Nakajima, Q. D. M. Khosru, T. Yoshimoto, T. Kidera, and S. Yokoyama, "Low-temperature formation of highly-reliable silicon-nitride gate dielectrics with suppressed soft-breakdown phenomena for advanced complementary metal-oxide-semiconductor technology," J. Vac. Sci. & Technol., Vol. B 20, pp. 1406-1409, 2002.

[02-88] A. Nakajima, T. Kidera, H.Ishii, and S. Yokoyama, "Atomic-layer deposition of ZrO2 with a Si nitiride barrier layer," Appl. Phys. Lett., Vol. 81, pp. 2824-2826, 2002.

[02-89] Q. D. M. Khosru, A. Nakajima, T. Yoshimoto, and S. Yokoyama, "Response to 'Comment on 'Reliable extraction of the energy distribution of Si/SiO2 interface traps in ultrathin metal-oxide-semiconductor structures' [Appl. Phys. Lett., Vol. 81, 3681]," Appl. Phys. Lett., Vol. 81, pp. 3683-3684, 2002.

[02-90] A. Nakajima, Q. D. M. Khosru, T. Yoshimoto, and S. Yokoyama, "Atomic-layer-deposited silicon-nitride/SiO2 stack - a highly potential gate dielectrics for advanced CMOS technology (Introductory Invited)," Microelectron. Reliab., Vol. 42, pp.1823-1835, 2002.

[02-91] A. Nakajima and S. Yokoyama, "Atomic-layer-deposition of Si nitride and ZrO2 for gate dielectrics (Invited)," Abst. AVS Topical Conference on Atomic Layer Deposition (ALD 2002), pp. 6-6, Seoul, August 19-21, 2002.

[02-92] Q. D. M. Khosru, A. Nakajima, T. Yoshimoto, and S. Yokoyama, "A novel method for extracting the energy distribution of Si/SiO2 interface traps in ultrathin oxide MOS structures," the Second IEEE Conference on Nanotechnology, Washington, D. C., August 26-28, 2002.

[02-93] Q. D. M. Khosru, A. Nakajima, and S. Yokoyama, "Time-dependent breakdown of ultrathin SiO2 gate dielectrics under static and dynamic stress," 2nd ECS Int. Semiconductor Technology Conf., Abs. No.71, Tokyo, September 11-14, 2002.

[02-94] H. Ishii, T. Kidera, A. Nakajima, and S. Yokoyama, "Atomic-layer deposition of ZrO2 with a Si nitiride barrier layer," Ext. Abst. Int. Conf. on Solid State Devices and Materials, pp. 452-453, Nagoya, September 17-19, 2002.

[02-95] Q. D. M. Khosru, A. Nakajima, and S. Yokoyama, "A comparative study of bulk and interface trap generation in ultrathin SiO2 and atomic-layer-deposited Si-nitride/SiO2 stack gate dielectrics," Forth Int. Symposium on Control of Semiconductor Interface (ISCSI-IV), pp. A6-3-A6-3, Karuizawa, October 21-25, 2002.

[02-96] Q. D. M. Khosru, A. Nakajima, and S. Yokoyama, "An Effective Method for Obtaining Interface Trap Distribution in MOS Capacitors with Tunneling Gate Oxides," Proc. IEEE Int. Conf. on Semiconductor Electronics (ICSE), pp. 402-406, Penang, December 19-21, 2002.

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2 Self-assembling techniques and quantum structures

2.1 Silicon quantum dots and quantum electronics

[02-97] Y. Ito, T. Hatano, A. Nakajima, and S. Yokoyama, "Fabrication of Si single-electron transistors having double SiO2 barriers," Appl. Phys. Lett., Vol. 80, pp. 4617-4619, 2002.

[02-98] A. Nakajima, Y. Ito, and S. Yokoyama, "Conduction mechanism of Si single-electron transistors having a one-dimensional regular array of multiple tunnel junctions," Appl. Phys. Lett. , Vol. 81, pp. 733-735, 2002.

[02-99] H. Sumitomo, M. Yamanishi, and Y. Kadoya, "Photon-number squeezing by the nonlinear backward pump process in a constant-voltage heterojunction LED," Phys. Rev. B 65, Art No. 165325, 2002.

[02-100] H. Sumitomo, M. Yamanishi, and Y. Kadoya, "Theory of photon-number squeezing in a heterojunction LED by the nonlinear backward pump process," Phys. Rev., B 65, Art No. 165326, 2002.

[02-101] Y. Darma, R. Takaoka, H. Murakami and S. Miyazaki, "Self-assembling formation of silicon quantum dots with a germanium core by low-pressure chemical vapor deposition," Nanotechnology, Vol. 14, pp. 413-415, 2002.

[02-102] Y. Darma, H. Murakami and S. Miyazaki, "Formation of Nanometer Silicon Dots with Germanium Core by Highly-Selective Low-Pressure Chemical Vapour Deposition," Intern. Microprocesses and Nanotechnology Conf., pp. 58-59 (7B-4-2), Tokyo, Nov. 6-8, 2002.

[02-103] M. Ikeda, Y. Shimizu, H. Murakami and S. Miyazaki, "Multiple-Step Electron Charging in Si Quantum-Dot Floating Gate MOS Memories," Intern. Microprocesses and Nanotechnology Conf., pp. 116-117(7Ｐ-7-10), Tokyo, Nov. 6-8, 2002.

[02-104] Y. Darma, R. Takaoka, H. Murakami and S. Miyazaki, "Self-Assembling Formation of Silicon Quantum Dot with Germanium Core by LPCVD," Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices, pp. 307-310(7.9), Sapporo, July 1-3, 2002.

[02-105] S. Miyazaki, "Self-Assembling of Si quantum Dots and Their Application to Memory Devices (Invited)," 2nd Vacuum & Surface Sciences Conference of Asia and Australia, No. 7, Hong Kong, August 26-30, 2002.

[02-106] S. Miyazaki, "Self-Assembling of Si Quantum Dots and Their Application to Memory Devices (Invited)," Intern. Conf. on Polycrystalline Semiconductors, I05, p. 56, Nara, Sept. 10-13, 2002.

[02-107] K. Takeuchi, H. Murakami and S. Miyazaki, "ELECTRONIC CHARGING STATE OF Si QUANTUM DOTS FORMED ON ULTRATHIN SiO2 AS EVALUATED BY AFM/KELVIN PROBE METHOD," Internat. Smiconductor Technology Conf., Abst. No.33, pp. 1-8, Tokyo, Sept. 12-14, 2002.

2.2 Nanoscale structures

[02-108] K. Kawamura, T. Kidera, A. Nakajima and S. Yokoyama, "Coulomb blockade effects and conduction mechanism in extremely thin polycrystalline-silicon wires," J. Appl. Phys. Lett. 91, No. 8, pp. 5213-5220, 2002.

[02-109] S. Shingubara, Y. Murakami, K. Morimoto, H. Sakaue, and T. Takahagi, "Formation of Al Nanodot Array by the Combination of Nano-Indentation and Anodic Oxidation," Mat. Res. Soc. Symp. Proc., Vol. 705, pp. 133-138, 2002.

[02-110] S. Shingubara, H. Murakami, H. Sakaue,and T. Takahagi, "Formation of Al Dot Hexagonal Array on Si Using Anodic Oxidation and Selective Etching," Jpn. J. Appl. Phys. Vol. 41, L340-343, 2002.

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3 Technologies for intelligent systems

[02-111] H. J. Mattausch, N. Omori, S. Fukae, T. Koide and T. Gyohten, "Fully-Parallel Pattern-Matching Engine with Dynamic Adaptability to Hamming or Manhattan Distance," Symposium on VLSI Circuits, Digest of Technical Papers, pp. 252-255, 2002.

[02-112] T. Koide, T. Morimoto, Y. Harada, H. J. Mattausch, "Digital Gray-Scale/Color Image-Segmentation Architecture for Cell-Network-Based Real-Time Applications," Proc. the International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), pp. 670-673, 2002.

[02-113] T. Morimoto, Y. Harada, T. Koide and H. J. Mattausch, "Real-Time Segmentation Architecture of Gray-Scale/Color Motion Pictures and Digital Test-Chip Implementation," Proc. the IEEE Asia-Pacific Conference on ASICs (AP-ASIC), pp. 37-240, 2002.

[02-114] T. Morimoto, Y. Harada, T. Koide and H. J. Mattausch, "Low-Complexity, Highly-Parallel Color Motion-Picture Segmentation Architecture for Compact Digital CMOS Implementation," Ext. Abst. the International Conference on Solid State Devices and Materials, pp. 242-243, 2002.

[02-115] Y. Yano, T. Koide and H. J. Mattausch, "Fully Parallel Nearest Manhattan-Distance-Search Memory With Large Reference-Pattern Number," Ext. Abst. the International Conference on Solid State Devices and Materials, pp. 254-255, 2002

[02-116] T. Koide, H. J. Mattausch, Y. Yano, T. Gyohten and Y. Soda, "A Nearest-Hamming-Distance Search Memory with Fully Parallel Mixed Digital-Analog Match Circuitry," Proc. the Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 591-592, Special Feature Award, University Design Contest, 2003.

[02-117] 中矢 真吾, 小出 哲士，若林 真一, "適応的遺伝的アルゴリズムに基づくVLSIフロアプランニングの一手法," 情報処理学会論文誌, Vol. 43, No. 5, pp. 1361-1371, 2002.

[02-118] S. Yamasaki, S. Nakaya, S. Wakabayashi, and T. Koide, "A Performance-Driven Floorplanning Method with Interconnect Performance Estimation," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E85-A, No. 12, pp. 2775-2784, 2002.

[02-119] 若林 真一, 小泉 慎哉, 小出 哲士, 井村 紀道, 藤原 一成, "遺伝的アルゴリズムの高速実行に適した命令セットを持つ専用RISCプロセッサDLX-GA," 情報処理学会論文誌, Vol. 44, No. 2, pp. 340-343, 2003.

[02-120] T. Morie, J. Umezawa, T. Nakano, H. Ando, M. Nagata, and A. Iwata, "A Biologically-Inspired Object Recognition System Using Pixel-Parallel Feature Extraction VLSIs," International Invitational Workshop on Intelligent Interface Devices, pp. 35-37, Kitakyushu, March 14, 2002.

[02-121] M. Nagata, T. Morie, and A. Iwata, "Modeling Substrate Noise Generation in CMOS Digital Integrated Circuits," IEEE 2002 Custom Integrated Circuit Conf., pp. 501-504, Orlando, May 2002.

[02-122] T. Morie, T. Matsuura, M. Nagata, and A. Iwata, "A multi-nanodot floating-gate MOSFET circuit for spiking neuron models," 2002 IEEE Silicon Nanoelectronics Workshop, pp. 53-54, Honolulu, June 9, 2002.

[02-123] T. Morie and T. Matsuura, M. Nagata and A. Iwata, "A Multi-Nano-Dot Circuit and Structure Using Thermal-Noise Assisted Tunneling for Stochastic Associative Processing," J. Nanosci. Nanotech., Vol. 2, No. 3, pp. 343-349, June, 2002.

[02-124] T. Morie, T. Matsuura, A. Iwata, and M. Nagata, "An Efficient Clustering Algorithm Using Stochastic Association Model and Its Implementation Using Nanostructures," Advances in Neural Information Processing Systems 14, Ed. T. G. Dietterich, S. Becker and Z. Ghahramani, pp. 1115-1122, MIT Press, Cambridge, MA, 2002.

[02-125] K. Katayama, M. Nagata, T. Morie and A. Iwata, "An Hadamard Transform Chip Using the PWM Circuit Technique and Its Application to Image Processing," IEICE Trans. Electron., Vol. E85-C, No. 8, pp. 1596-1603, Aug. 2002.

[02-126] K. Katayama and A. Iwata, "A High-Resolution Hadamard Transform Chip," Ext. Abst. of International Conference on Solid State Devices and Materials, pp. 372-373, Nagoya, Sept. 17-19, 2002.

[02-127] T. Maeda, A. Iwata, M. Kawabata, and S. Orisaka, "A 10-GHz Bipolar VCO with Reduced Phase Noise," Ext. Abst. International Conference on Solid State Devices and Materials, pp. 370-371, Nagoya, Sept.17-19, 2002.

[02-128] 岩田　穆, "高機能アナログ・ディジタル混載システムLSI技術," 電子情報通信学会論文誌, Vol. J85-C, No. 9, 2002年9月.

[02-129] H. Ando, T. Morie, M. Nagata, and A. Iwata, "An Image Region Extraction LSI Based on a Merged/mixed-signal Nonlinear Oscillator Network Circuit," 28th European Solid-State Circuits Conference (ESSCIRC), Abs. No. CP. 11, pp. 703-706, Florence, Italy, Sept. 26, 2002.

[02-130] K. Katayama and A. Iwata, "Pulse Coupled Neural Network using Coupled Phase Locked Loop, International Symposium on Nonlinear Theory and its Applications (NOLTA)," pp. 853-856, Xi'an, October 7-11, 2002

[02-131] T. Morie, T. Matsuura, M. Nagata, and A. Iwata, "An Efficient Clustering Algorithm Using Stochastic Association and Its Implementation Using 3D-Nanodot-Array Structures (Invited), " RCIQE International Seminar on "Quantum Nanoelectronics for Meme-Media- Based Information Technologies," pp. 59-63, Sapporo, Feb. 13, 2003.