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2001 (2001 April - 2002 March)

  1. Advanced device process and material technologies for ULSI
  2. Self assembling technique and quantum structure
  3. Technologies for intelligent systems

1 Advanced device process and material technologies for ULSI

1.1 Fabrication techniques for scaled MOS devices

[01-1] K. Shibahara, "Doping Issues for sub-100 nm MOSFETs," Proc. of 2001 Korea-Japan Joint Workshop on Advanced Semionductor Processes and Equipments (APSE2001), pp. 160-164, 2001.

[01-2] D. Onimatsu and K. Shibahara, "Influence of Extension Formation Process o Indium Halo Profile," Extend. Abst. of the Int. Conf. on Solid State Devices and Materials (SSDM2001), pp. 184-185, 2001

[01-3] K. Shibahara, Y. Ishikawa, D. Onimatsu, N. Maeda, A. Mineji, K. Kagawa, A. Matuno, and T. Nire, "Antimony Behavior in Laser Annealing Process for Ultra Shallow Junction Formation," Extend. Abst. of the Int. Conf. on Solid State Devices and Materials (SSDM2001), pp. 236-237, 2001

[01-4] K. Shibahara, T. Oda, and T. Kikkawa, "Copper Drift in Low Dielectric Constant Insulator Films Caused by O2+ Primary Ion Beam," Abst. 13th Int. Conf. on Secondary Ion Mass Spectrometry and Related Topics (SIMSXIII), p. 37, 2001

[01-5]N. Kawakami, K. Egusa, and K. Shibahara, "Reduction of Threshold Voltage Fluctuation of p-MOSFETs by Antimony Super Steep Retrgrade Well Channel," Ext. Abst. the 2nd Int. Workshop on Junction Technology 2001 (IWJT2001), pp. 7-10, 2001.

1.2 Evaluation and modeling techniques for scaled MOS devices

[01-6] M. Miura-Mattausch, M. Suetake, H. J. Mattausch, S. Kumashiro, N. Shigio, S. Odanaka, and N. Nakayama, "Physical Modeling of the Reverse-Short-Channel Effect for Circuit Simulation," IEEE Trans. on Electron Devices, Vol 48, pp. 2449-2452, 2001.

[01-7] S. Matsumoto, H. J. Mattausch, S. OOshiro, Y. Tatsumi, M. Miura-Mattausch, S. Kumashiro, T. Yamaguchi, K. Yamashita and N. Nakayama, "Test-Circuit-Based Extraction of Inter- and Intra-Chip MOSFET-Performance Variations for Analog-Design Reliability," Proc. of the IEEE Custom Integrated Circuits Conference (CICC2001), pp. 357-360, 2001.

[01-8] D. Kitamaru, H. Ueno, K. Morikawa, M. Tanaka, M. Miura-Mattausch, H. J. Mattausch. S. Kumashiro, T. Yamaguchi, K. Yamashita and N. Nakayama, "Vth-Model of Pocket-Implant MOSFETs for Circuit Simulation," Proc. of the Int. Conf. on Simulation of Semiconductor Processes and Devices (SISPAD2001), pp. 392-395, 2001

[01-9]K. Morikawa, H. Ueno, D. Kitamaru, M. Tanaka, T. Okagaki, M. Miura-Mattausch, H. J. Mattausch, S. Kumashiro, T. Yamaguchi, K. Yamashita and N. Nakayama, "Enhanced Quantum Effect for Sub-0.1um Pocket Technologies and its Relevance for the On-Current Condition," Extend. Abst. of the Int. Conf. on Solid State Devices and Materials (SSDM2001), p. 384-385, 2001

[01-10] H. J. Mattausch, M. Miura-Mattausch, H. Ueno, S. Kumashiro, T. Yamaguchi, K. Yamashita and N. Nakayama, "HiSIM: The First Complete Drift-Diffusion MOSFET Model for Circuit Simulation," Proc. of the Int. Conf. on Solid-State and Inegrated-Circuit Technology (ICSICT2001), pp. 861-866, 2001, (Invited Paper).

[01-11] M. Miura-Mattausch, H. J. Mattausch, N. D. Arora, and C. Y. Yang, "MOSFET Modeling Gets Physical," IEEE Circuits and Devices Magazine, Vol. 17, pp. 29-36, 2001.

1.3 Gate oxide and reliability issues

[01-12] W. Mizubayashi, Y. Yoshida, S. Miyazaki, and M. Hirose, "Analysis of Oxide Voltage and Field Depedences of Time-Dependent Dielectric Soft Breakdown in Ultra Gate Oxides," Extend. Abst. of the Int. Conf. on Solid State Devices and Materials (SSDM2001), pp. 210-211, 2001.

[01-13] W. Mizubayashi, Y. Yoshida, S. Miyazaki, and M. Hirose, "Statistical Analysis of Soft Breakdown in Ultrathin Gate Oxides, " 2001 Symposium on VLSI Technology, pp. 95-96, 2001.

1.4 Interconnect technologies

[01-14] S. Yokoyama, Y. Hara, and K. Umeda, "Stachked Optical Branched Waveguides for Optical Interconnection on Si Chips," Extend. Abst. of the Int. Conf. on Solid State Devices and Materials (SSDM2001), pp. 596-597, 2001.

[01-15] S. Shingubara, S. Miyazaki, H. Sakaue, and T. Takahagi, "Evaluation of Temperature Rise Due to Joule Heating and Preliminary Investigation of It's Effect on Electromigration Reliability," American Inst. of Phys. Conf. Proc., Vol. 612, "Stress Induced Phenomena in Metallization Sixth Workshop," pp. 94-104, 2002.

[01-16] S. Shingubara, T. Ida, H. Sawa, H. Sakaue, and T. Takahagi, "Effect of Pd Catalyst Adsorption on Cu Filling Characteristics in Electroless Plating," Proc. of Advanced Metallization Conf. 2000, Mat. Res. Soc. ULSI-XVI, pp. 229-234, 2001.

1.5 CVD and Si epitaxial technologies

[01-17] H. Habuka, M. Shimada, and K. Okuyama, "Adsorption and Desorption Rate of Multicomponent Organic Species on Silicon Wafer Surface, " J. Electrochem. Soc., Vol. 148, No. 7, pp. 365-369, 2001.

[01-18] Setywan, M. Shimada, K. Ohtsuka, and K. Okuyama, "Visualization and Numerical Simulation of Fine Particle Transport in a Low-Pressure Parallel Plate Chemical Vapor Deposition Reactor," Chem. Eng. Sci., Vol. 57, No. 3, pp. 497-506, 2002.

[01-19] Setywan, M. Shimada, and K. Okuyama, "Characterization of Fine Particle Trapping in Plasma-Enhanced Chemical Vapor Deposition Reactor," J. Appl. Phys., 2002.

1.6 Atomic scale process

[01-20] S. Yokoyama, K. Ohba, K. Kawamura, T. Kidera and A. Nakajima "Low-Temperature Selective Deposition of Silicon on Silicon Nitride by Time-Modulated Disilane Flow and Formation of Silicon Narrow Wires," Appl. Phys. Lett. Vol. 79, pp. 494-496, 2001.

[01-21] S. Yokoyama, K. Ohba, and A. Nakajima "Self-Limiting Atomic-Layer Deposition of Si SiO2 by Alternate Supply of Si2H6 and SiCl4," Appl. Phys. Lett. Vol. 79, pp. 617-619, 2001.

[01-22] A. Nakjima, T. Yoshimoto, T. Kidera, and S. Yokoyama, "Low-temperature formation of silicon nitride gate dielectrics by atomic-layer deposition, " Appl. Phys. Lett. Vol. 79, pp. 665-667, 2001.

[01-23] A. Nakjima, T. Yoshimoto, T. Kidera, K. Obata, S. Yokoyama, H. Sunami, and M. Hirose "Characterization of atomic-layer-deposited silicon nitride/SiO2 staked gate dielectrics for highly reliable p-metal-oxide-semiconductor field-effect transistors," J. Vac. Sci. & Technol. B Vol. 19, pp. 1138-1143, 2001.

[01-24] Q. D. M. Khosru, A. Nakajima, T. Yoshimoto, and S. Yokoyama, "Soft-breakdown-suppressed ultrathin atomic-layer-deposited silicon nitride/SiO2 staked gate dielectrics for advanced complementary metal-oxide-semiconductor technology," Appl. Phys. Lett. Vol. 79, pp. 3488-3490, 2001.

[01-25] A. Nakajima, Q. D. M. Khosru, T. Yoshimoto, T. Kidera, and S. Yokoyama, "NH3-annealed atomic-layer-deposited silicon nitride as a high-k gate dielectric with high reliability," Appl. Phys. Lett. Vol. 80, pp. 1252-1254, 2002.

[01-26] A. Nakajima, Q. D. M. Khosru, T. Yoshimoto, T. Kidera, and S. Yokoyama, "Soft breakdown free atomic-layer-deposited silicon-nitride/SiO2 stack gate dielectrics," Technical Digest of the 2001 IEEE Int. Electron Devices Meeting (IEDM2001), pp. 133-136, 2001.

[01-27] Q. D. M. Khosru, A. Nakajima, T. Yoshimoto, and S. Yokoyama, "Ultrathin NH3 annealed atomic layer deposited Si-nitride/SiO2 stack gate dielectrics with high reliablity," 2001 Int. Semiconductor Devices Research Symposium, pp. 26-29, 2001.

1.7 Low-k interlayer dielectric films

[01-28] T. Kikkawa, " A photosensitive low-k interlayer-dielectric film for ULSIs," Proc. of Int. Conf. on Solid-State and Integrated Circuit Technology, pp. 348-351, 2001, (Invited).

[01-29] T. Kikkawa, "Current and Future Low-k/Cu Interconnect Technologies for ULSIs," Proc. Workshop on Frontiers in Electronics, p. 25, 2002 (Invited).

[01-30] T. Kikkawa and T. Oda, "Influence of copper ion drift on leakage current in porous methylsilsesquioxane derived from methylpolysilazne," Proc. of European Workshop on Materials for Advanced Metallization, 2002

[01-31] H. Sakaue, Y. Yoshimura, S. Shingubara, and T. Takahagi, "Low Dielectric Constant Porous Diamond Film Composed of Diamond Nano-Particles," Proc. of Advanced Metallization Conf. 2000, Mat. Res. Soc. ULSI-XVI, pp. 647-652, 2001.

[01-32] K. Yamada, A. Saiki, S. Sakaue, S. Shingubara, and T. Takahagi, "Study of dielectric constant due to electronic polarization using a semiemperical molecular orbital method," Jpn. J. Appl. Phys. 40, pp. 4829-2836, 2001.

1.8 High-k dielectrics

[01-33] S. Miyazaki, "Electronic Structures of High-k Gate Dielectrics," Frontier Sci. Res. Conf. in Mat. Sci. & Technol. Series: Sci. & Technol. of Silicon Materials, pp. 44-47, 2001, (Invited).

[01-34] S. Miyazaki, "Electronic Structures of High-k Gate Dielectrics," Bulletin of th Stefan Univ., Vol. 13, No. 13, pp. 44-47, 2001.

[01-35] S. Miyazaki and M. Hirose, "Photoemission Study of Energy Band Alignment and Gap State Density Distrubution for High-k Gate Dielectrics," American Inst. of Phys. Conf. Proc., Vol. 550, pp. 89-96, 2001.

[01-36] S. Miyazaki, "Chemical and Electronic Structures of Ultrathin High-k Dielectrics and the Dielectric/Silicon Interfaces," Sixth China-Japan Symposium on Thin Films, pp. 69-73, 2001.

[01-37] S. Miyazaki, "Characterization of Ultrathin Gate Dielectrics on Silicon by Photoelectron Spectrocopy," Int. Workshop on Devices Technology - Alternatives on to SiO2 as Gate Dielectrics for Future Si-Based Microelectronics, p. 19, 2001, (Invited).

[01-38] S. Miyazaki, M. Narasaki, M. Ogasawara, and M. Hirose, "Characterization of Ultrathin Zirconium Oxide Films on Silicon Using Photoelectrons Spectroscopy," Insulating Films on Semiconductors, 12th Bi-annual Conf., pp. 127-128, 2001.

[01-39] S. Miyazaki, "Characterization of High-k Gate Dielectric/Silicon Interface," Proc. of the 8th Intern. Conf. on the Formation of Semiconductor Interfaces, p. 190, 2001, (Invited).

[01-40] S. Miyazaki, M. Narasaki, M. Ogasawara, and M. Hirose, "Characterization of Ultrathin Zirconium Oxide Films on Silicon Using Photoelectrons Spectroscopy," Microelec. Eng., Vol. 59, No. 1-4, pp. 373-378, 2001.

[01-41] S. Miyazaki, "Photoemission Study of Energy-band Alignments and Gap-state Density Distributions for Higt-k Gate Dielectrics," J. Vac. Sci. Technol. B, Vol. 19, No. 6, pp. 2212-2216, 2001.

[01-42] H. Yamashita, W. Mizubayashi, H. Murakami, and S. Miyazaki, "Impact on Nitrogen Incorporation in Ultrathin SiO2 on the Chemical and Electonic Structures of the SiO2/Si(100) Interface," Ext. Abst. of Int. Workshop on Gate Insulator 2001 (IWGI2001), pp. 224-225, 2001.

1.9 Contamination control

[01-43] T. Yoshino, S. Yokoyama, and T. Fujii, "Effect of Light Irradiation on Native Oxidation of Silicon Surface," Jpn. J. Appl. Phys. Vol. 40, No. 4A, pp. 2223-2224, 2001.

[01-44] T. Yoshino, S. Yokoyama, T. Suzuki, and T. Fujii, "Influence of Organic Contaminant on Breakdown Characteristics of MOS Capacitors with Thin SiO2," Jpn. J. Appl. Phys. Vol. 40, No. 4B, pp. 2849-2853, 2001.

[01-45] T. Yoshino, S. Yokoyama, T. Fujii, K. Shibahara, A. Nakajima, T. Kikkawa, H. Sunami, and Q. D. M. Khosru, "Influence of Organic Contaminantion on Reliability and Trap Generation in MOS Devices," Extend. Abst. of the Int. Conf. on Solid State Devices an Materials (SSDM2001), pp. 176-177, 2001.

[01-46] H. Habuka, T. Otsuka, W. F. Qu, M. Shimdada, and K. Okuyama, "Model of Boron Incorporation into Silicon Epitaxial Film in a B2H6-SiHCl3-H2 System," J. Cryst. Crowth, Vol. 222, No. 1-2, pp. 183-193, 2001.

[01-47] M. Shimada, H. Chang, Y. Fujishige, and K. Okuyama, "Calibration of Polarization-Sensitive and Dual-Angle Laser Light Scattering Methods using Standard Latex Particles," J. Colloid Interface Sci., Vol. 241, No. 1, pp. 71-80, 2001.

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2 Self assembling technique and quantum structure

2.1 Si quantum dot

[01-48] M. Ikeda, E. Yoshida, A. Kohno, S. Miyazaki, and M. Hirose, "Charge Injection Characteristics of a Si Quantum Dot Floating Gate in MOS Structure," Extend. Abst. of the Int. Conf. on Solid State Devices an Materials (SSDM2001), pp. 308-309, 2001.

[01-49] A. Kohno, H. Murakami, M. Ikeda, S. Miyazaki, and M. Hirose, "Memory Operation of Silicon Quantum-Dot Floating Gate Metal-Oxide-Semiconductor Field-Effect Transistors," Jpn. J. Appl. Phys. Vol. 40, No. 7B, pp. L721-L723, 2001.

[01-50] S. Miyazaki, M. Ikeda, E. Yoshida, N. Shimizu, and M. Hirose, "Nucleation Site Control in Self-Assembling of Si Quantum Dots on Ultrathin SiO2/c-Si," Springer Proc. in Phys. 87: Proc. of 25th Intern. Conf. on the Physics of Semiconductor, Vol. 19, No. 6, pp. 373-374, 2001.

2.2 Al nanoscale structure

[01-51] K. Kawamura, T. Kidera, A. Nakajima, and S. Yokoyama, "Conduction mechaism in extremely thin poly-Si wires ---width dependence of Coulomb blockade effect---," Extend. Abst. of the Int. Conf. on Solid State Devices an Materials (SSDM2001), pp. 438-439, 2001.

[01-52] S. Shingubara, O. Okino, H. Sakaue, and T. Takahagi, "Fabrication of Nanohole Array on Si Using Self-Organized Porous Alumina Mask," J. Vac. Sci. Technol. B 19, pp. 1901-1904, 2001.

[01-53] H. Sakaue, S. Fujiwara, S. Shingubara, and T. Takahagi, "Atomic-scale defect control on hydrogen-terminated silicon surface at wafer scale," Appl. Phys. Lett. 86. 309-311, 2001.

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3 Technologies for intelligent systems

[01-54] N. Omori and H. J. Mattausch, "Compact central arbiters for memories with multiple ports," IEE Electronics Letters, Vol. 37, pp. 811-813, 2001.

[01-55] H. J. Mattausch, T. Gyohten, Y. Soda, T. Koide, "Compact Associative-Memory Architecture with Fully-Parallel Search Capability for the Minimum Hamming Distance," IEEE Journal of Solid-State Circuits, Vol. 37, pp. 218-227, 2002.

[01-56] S. Kinoshita, T. Morie, M. Nagata and A. Iwata, "A PWM Analog Memory Programming Circuit for Floating-Gate MOSFETs with 75us Programming Time and 11b Updating Resolution," IEEE J. Solid-State Circuits, Vol. 36, No. 8, pp. 1286-1290, August 2001.

[01-57] T. Yamanaka, T. Morie, M. Nagata, and A. Iwata, "A CMOS Stochastic Associative Processor Using PWM Chaotic Signal," IEICE Trans. Electronics, Vol. E84-C, No. 12, pp. 1723-1729, 2001.

[01-58] M. Nagata, T. Ohmoto, Y. Murasaka, T. Morie, and A. Iwata, "Effects of Power-Supply Parasitic Components on Substrate Noise Generation in Large-Scale Digital Circuits," Symp. on VLSI Circuits, pp. 159-162, 2001.

[01-59] A. Iwata, T. Morie, and M. Nagata, "Bio-Inspired VLSIs Based on Analog/Digital Merged Technologies," Extend. Abst. of the Int. Conf. on Solid State Devices and Materials (SSDM2001), pp. 88-89, 2001, (Invited).

[01-60] T. Morie, M. Miyake, M. Nagata, and A. Iwata, "A I-D CMOS PWM Cellular Neural Network Circuit and Resistive-Fuse Network Operation," Extend. Abst. of the Int. Conf. on Solid State Devices and Materials (SSDM2001) pp. 90-91, 2001, pp. 88-89, 2001

[01-61] T. Morie, M. Nagata, and A. Iwata, "Design of a Pixel-Parallel Feature Extraction VLSI System for Biologically-Inspired Object Recognition Methods," Proc. of Int. Symposium on Nonlinear Theory and its Application (NOLTA2001), pp. 371-374, 2001.

[01-62] S. Koizumi, S. Wakabayashi, T. Koide, K. Fujiwara, and N. Imura, "A RISC Architecture for high-speed execution of generic algorithms," Proc. of 2001 Genetic and Evolutionary Computation Conf. (GECCO-2001), pp. 1338-1345, 2001.

[01-63] N. Toshine, N. Iwauchi, S. Wakabayashi, T. Koide, and I. Nishimura, "A parallel genetic algorithm with adaptive adjustment of genetic parameters," Proc. of 2001 Genetic and Evolutionary Computation Conf. (GECCO-2001), pp. 679-686, 2001.

[01-64] S. Nakaya, S. Yamasaki, S. Wakabayashi, and T. Koide, "A performance-driven floorplanning method with precise area and interconnect delay estimation with wire sizing and buffer insertion," Proc. of the 10th Workshop on Synthesis And System Integration of Mixed Technologies (SASIMI 2001), pp. 226-233, 2001.